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gpu: nvgpu: split ltc fusa/non-fusa hal

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Moved gv11b_ltc_inject_ecc_error from ltc_gv11b to fusa version.
Moved debugger related functions from ltc_gm20b to fusa version.
Updated the arch yaml to reflect the non-fusa and fusa units
for ltc units.

JIRA NVGPU-3690

Change-Id: I48e360f18da760907e733023e013bd039ba5cca4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156878
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-07-19 11:22:54 +05:30
committed by mobile promotions
parent e3686b5c07
commit 5da58b3246
6 changed files with 134 additions and 129 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
arch/nvgpu-hal-new.yaml
View File

@@ -15,29 +15,34 @@ bus:
hal/bus/bus_tu104.c, hal/bus/bus_tu104.h ]
ltc:
safe: yes
owner: Seshendra G
children:
ltc:
sources: [ hal/ltc/ltc_gm20b.c,
hal/ltc/ltc_gm20b_fusa.c,
ltc_fusa:
safe: yes
sources: [ hal/ltc/ltc_gm20b_fusa.c,
hal/ltc/ltc_gm20b.h,
hal/ltc/ltc_gp10b.c,
hal/ltc/ltc_gp10b_fusa.c,
hal/ltc/ltc_gp10b.h,
hal/ltc/ltc_gv11b.c,
hal/ltc/ltc_gv11b_fusa.c,
hal/ltc/ltc_gv11b.h,
hal/ltc/ltc_gv11b.h ]
ltc:
safe: no
sources: [ hal/ltc/ltc_gm20b.c,
hal/ltc/ltc_gp10b.c,
hal/ltc/ltc_gv11b.c,
hal/ltc/ltc_tu104.c,
hal/ltc/ltc_tu104.h ]
intr:
sources: [ hal/ltc/intr/ltc_intr_gm20b.c,
hal/ltc/intr/ltc_intr_gm20b.h,
hal/ltc/intr/ltc_intr_gp10b.c,
hal/ltc/intr/ltc_intr_gp10b_fusa.c,
intr_fusa:
safe: yes
sources: [ hal/ltc/intr/ltc_intr_gp10b_fusa.c,
hal/ltc/intr/ltc_intr_gp10b.h,
hal/ltc/intr/ltc_intr_gv11b_fusa.c,
hal/ltc/intr/ltc_intr_gv11b.h ]
intr:
safe: no
sources: [ hal/ltc/intr/ltc_intr_gm20b.c,
hal/ltc/intr/ltc_intr_gm20b.h,
hal/ltc/intr/ltc_intr_gp10b.c ]
init:
safe: yes

6
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -149,9 +149,6 @@ srcs += common/utils/enabled.c \
hal/init/hal_gv11b_litter.c \
hal/init/hal_init.c \
hal/power_features/cg/gv11b_gating_reglist.c \
hal/ltc/ltc_gm20b.c \
hal/ltc/ltc_gv11b.c \
hal/ltc/intr/ltc_intr_gm20b.c \
hal/fb/fb_gm20b.c \
hal/fb/fb_gv11b.c \
hal/fb/intr/fb_intr_ecc_gv11b.c \
@@ -285,6 +282,9 @@ srcs += hal/init/hal_gp10b.c \
hal/therm/therm_gm20b.c \
hal/therm/therm_gp10b.c \
hal/ltc/ltc_gp10b.c \
hal/ltc/ltc_gm20b.c \
hal/ltc/ltc_gv11b.c \
hal/ltc/intr/ltc_intr_gm20b.c \
hal/ltc/intr/ltc_intr_gp10b.c \
hal/fb/fb_gp10b.c \
hal/fb/fb_gp106.c \

96
drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c
View File

@@ -169,99 +169,3 @@ void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled)
gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg);
}
#ifdef CONFIG_NVGPU_DEBUGGER
/*
* LTC pri addressing
*/
bool gm20b_ltc_pri_is_ltc_addr(struct gk20a *g, u32 addr)
{
return ((addr >= ltc_pltcg_base_v()) && (addr < ltc_pltcg_extent_v()));
}
bool gm20b_ltc_is_ltcs_ltss_addr(struct gk20a *g, u32 addr)
{
u32 ltc_shared_base = ltc_ltcs_ltss_v();
u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
if (addr >= ltc_shared_base) {
return (addr < nvgpu_safe_add_u32(ltc_shared_base, lts_stride));
}
return false;
}
bool gm20b_ltc_is_ltcn_ltss_addr(struct gk20a *g, u32 addr)
{
u32 lts_shared_base = ltc_ltc0_ltss_v();
u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
u32 addr_mask = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE) - 1U;
u32 base_offset = lts_shared_base & addr_mask;
u32 end_offset = nvgpu_safe_add_u32(base_offset, lts_stride);
return (!gm20b_ltc_is_ltcs_ltss_addr(g, addr)) &&
((addr & addr_mask) >= base_offset) &&
((addr & addr_mask) < end_offset);
}
static void gm20b_ltc_update_ltc_lts_addr(struct gk20a *g, u32 addr,
u32 ltc_num, u32 *priv_addr_table, u32 *priv_addr_table_index)
{
u32 num_ltc_slices = g->ops.top.get_max_lts_per_ltc(g);
u32 index = *priv_addr_table_index;
u32 lts_num;
u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
for (lts_num = 0; lts_num < num_ltc_slices;
lts_num = nvgpu_safe_add_u32(lts_num, 1U)) {
priv_addr_table[index] = nvgpu_safe_add_u32(
ltc_ltc0_lts0_v(),
nvgpu_safe_add_u32(
nvgpu_safe_add_u32(
nvgpu_safe_mult_u32(ltc_num, ltc_stride),
nvgpu_safe_mult_u32(lts_num, lts_stride)),
(addr & nvgpu_safe_sub_u32(
lts_stride, 1U))));
index = nvgpu_safe_add_u32(index, 1U);
}
*priv_addr_table_index = index;
}
void gm20b_ltc_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
u32 *priv_addr_table,
u32 *priv_addr_table_index)
{
u32 num_ltc = g->ltc->ltc_count;
u32 i, start, ltc_num = 0;
u32 pltcg_base = ltc_pltcg_base_v();
u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
for (i = 0; i < num_ltc; i++) {
start = nvgpu_safe_add_u32(pltcg_base,
nvgpu_safe_mult_u32(i, ltc_stride));
if (addr >= start) {
if (addr < nvgpu_safe_add_u32(start, ltc_stride)) {
ltc_num = i;
break;
}
}
}
gm20b_ltc_update_ltc_lts_addr(g, addr, ltc_num, priv_addr_table,
priv_addr_table_index);
}
void gm20b_ltc_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
u32 *priv_addr_table,
u32 *priv_addr_table_index)
{
u32 num_ltc = g->ltc->ltc_count;
u32 ltc_num;
for (ltc_num = 0; ltc_num < num_ltc; ltc_num =
nvgpu_safe_add_u32(ltc_num, 1U)) {
gm20b_ltc_update_ltc_lts_addr(g, addr, ltc_num,
priv_addr_table, priv_addr_table_index);
}
}
#endif /* CONFIG_NVGPU_DEBUGGER */

96
drivers/gpu/nvgpu/hal/ltc/ltc_gm20b_fusa.c
View File

@@ -42,6 +42,102 @@
#include "ltc_gm20b.h"
#ifdef CONFIG_NVGPU_DEBUGGER
/*
* LTC pri addressing
*/
bool gm20b_ltc_pri_is_ltc_addr(struct gk20a *g, u32 addr)
{
return ((addr >= ltc_pltcg_base_v()) && (addr < ltc_pltcg_extent_v()));
}
bool gm20b_ltc_is_ltcs_ltss_addr(struct gk20a *g, u32 addr)
{
u32 ltc_shared_base = ltc_ltcs_ltss_v();
u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
if (addr >= ltc_shared_base) {
return (addr < nvgpu_safe_add_u32(ltc_shared_base, lts_stride));
}
return false;
}
bool gm20b_ltc_is_ltcn_ltss_addr(struct gk20a *g, u32 addr)
{
u32 lts_shared_base = ltc_ltc0_ltss_v();
u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
u32 addr_mask = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE) - 1U;
u32 base_offset = lts_shared_base & addr_mask;
u32 end_offset = nvgpu_safe_add_u32(base_offset, lts_stride);
return (!gm20b_ltc_is_ltcs_ltss_addr(g, addr)) &&
((addr & addr_mask) >= base_offset) &&
((addr & addr_mask) < end_offset);
}
static void gm20b_ltc_update_ltc_lts_addr(struct gk20a *g, u32 addr,
u32 ltc_num, u32 *priv_addr_table, u32 *priv_addr_table_index)
{
u32 num_ltc_slices = g->ops.top.get_max_lts_per_ltc(g);
u32 index = *priv_addr_table_index;
u32 lts_num;
u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
for (lts_num = 0; lts_num < num_ltc_slices;
lts_num = nvgpu_safe_add_u32(lts_num, 1U)) {
priv_addr_table[index] = nvgpu_safe_add_u32(
ltc_ltc0_lts0_v(),
nvgpu_safe_add_u32(
nvgpu_safe_add_u32(
nvgpu_safe_mult_u32(ltc_num, ltc_stride),
nvgpu_safe_mult_u32(lts_num, lts_stride)),
(addr & nvgpu_safe_sub_u32(
lts_stride, 1U))));
index = nvgpu_safe_add_u32(index, 1U);
}
*priv_addr_table_index = index;
}
void gm20b_ltc_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
u32 *priv_addr_table,
u32 *priv_addr_table_index)
{
u32 num_ltc = g->ltc->ltc_count;
u32 i, start, ltc_num = 0;
u32 pltcg_base = ltc_pltcg_base_v();
u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
for (i = 0; i < num_ltc; i++) {
start = nvgpu_safe_add_u32(pltcg_base,
nvgpu_safe_mult_u32(i, ltc_stride));
if (addr >= start) {
if (addr < nvgpu_safe_add_u32(start, ltc_stride)) {
ltc_num = i;
break;
}
}
}
gm20b_ltc_update_ltc_lts_addr(g, addr, ltc_num, priv_addr_table,
priv_addr_table_index);
}
void gm20b_ltc_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
u32 *priv_addr_table,
u32 *priv_addr_table_index)
{
u32 num_ltc = g->ltc->ltc_count;
u32 ltc_num;
for (ltc_num = 0; ltc_num < num_ltc; ltc_num =
nvgpu_safe_add_u32(ltc_num, 1U)) {
gm20b_ltc_update_ltc_lts_addr(g, addr, ltc_num,
priv_addr_table, priv_addr_table_index);
}
}
#endif /* CONFIG_NVGPU_DEBUGGER */
/*
* Performs a full flush of the L2 cache.
*/

18
drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c
View File

@@ -34,24 +34,6 @@
#include <nvgpu/utils.h>
int gv11b_ltc_inject_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
u32 ltc = (error_info & 0xFF00U) >> 8U;
u32 lts = (error_info & 0xFFU);
u32 reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc, ltc_stride),
nvgpu_safe_mult_u32(lts, lts_stride)));
nvgpu_info(g, "Injecting LTC fault %s for ltc: %d, lts: %d",
err->name, ltc, lts);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
#ifdef CONFIG_NVGPU_GRAPHICS
/*
* Sets the ZBC stencil for the passed index.

18
drivers/gpu/nvgpu/hal/ltc/ltc_gv11b_fusa.c
View File

@@ -34,6 +34,24 @@
#include <nvgpu/utils.h>
int gv11b_ltc_inject_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
u32 ltc = (error_info & 0xFF00U) >> 8U;
u32 lts = (error_info & 0xFFU);
u32 reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc, ltc_stride),
nvgpu_safe_mult_u32(lts, lts_stride)));
nvgpu_info(g, "Injecting LTC fault %s for ltc: %d, lts: %d",
err->name, ltc, lts);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
static inline u32 ltc0_lts0_l1_cache_ecc_control_r(void)
{
return ltc_ltc0_lts0_l1_cache_ecc_control_r();