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gpu: nvgpu: remove non stall intr from top handler for safety

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On safety nonstall interrupt is not used and should be compiled out to
rule out any chance of interference with safety code. Remove top handler
support of nonstall interrupt for safety which is currently not
applicable to linux.

Jira NVGPU-7066
Jira NVGPU-4078

Change-Id: I278efc8da6ddd0f22c128af6630cfd1b20ba4784
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2589006
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2671586
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Shashank Singh
2021-09-03 13:02:52 +00:00
committed by mobile promotions
parent ca27a7d841
commit 5ec241a1d8
15 changed files with 65 additions and 13 deletions
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17
userspace/units/mc/nvgpu-mc.c
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -329,7 +329,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
unit_return_fail(m, "failed to disable stall intr for unit %u val=0x%08x\n",
unit, val);
}
#ifdef CONFIG_NVGPU_NONSTALL_INTR
/* enable nonstall intr */
nvgpu_cic_mon_intr_nonstall_unit_config(g, unit, true);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
@@ -345,6 +345,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
unit_return_fail(m, "failed to disable nonstall intr for unit %u val=0x%08x\n",
unit, val);
}
#endif
}
for (i = 0; i < ARRAY_SIZE(invalid_units); i++) {
@@ -366,6 +367,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
val);
}
#ifdef CONFIG_NVGPU_NONSTALL_INTR
/* negative testing - invalid unit enable set - nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0); /* clear en reg */
nvgpu_cic_mon_intr_nonstall_unit_config(g, invalid_units[i], true);
@@ -383,6 +385,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
unit_return_fail(m, "Incorrectly enabled non-stall interrupt for invalid unit, val=0x%08x\n",
val);
}
#endif
}
return UNIT_SUCCESS;
@@ -392,7 +395,9 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
{
u32 val;
u32 expected_stall_val = mc_intr_priv_ring_pending_f();
#ifdef CONFIG_NVGPU_NONSTALL_INTR
u32 expected_nonstall_val = mc_intr_pbus_pending_f();
#endif
void (*save_func)(struct gk20a *g);
/* clear regs */
@@ -410,7 +415,9 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* enable something to pause and resume */
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING, true);
#ifdef CONFIG_NVGPU_NONSTALL_INTR
nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, true);
#endif
/* pause stall */
nvgpu_cic_mon_intr_stall_pause(g);
@@ -419,12 +426,14 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
unit_return_fail(m, "failed to pause stall intr\n");
}
#ifdef CONFIG_NVGPU_NONSTALL_INTR
/* pause nonstall */
nvgpu_cic_mon_intr_nonstall_pause(g);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != 0) {
unit_return_fail(m, "failed to pause nonstall intr\n");
}
#endif
/* resume stall */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_SET_REG, 0x0);
@@ -434,6 +443,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
unit_return_fail(m, "failed to resume stall intr\n");
}
#ifdef CONFIG_NVGPU_NONSTALL_INTR
/* resume nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_SET_REG, 0x0);
nvgpu_cic_mon_intr_nonstall_resume(g);
@@ -441,10 +451,13 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
if (val != expected_nonstall_val) {
unit_return_fail(m, "failed to resume nonstall intr\n");
}
#endif
/* clear regs */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_CLEAR_REG, 0x0);
#ifdef CONFIG_NVGPU_NONSTALL_INTR
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_CLEAR_REG, 0x0);
#endif
/* mask all */
nvgpu_cic_mon_intr_mask(g);