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gpu: nvgpu: Use sw ops for PMU PG unit
Some functions are not accessing hardware directly but are being called using HAL ops: For example g->ops.pmu.pmu_elpg_statistics, g->ops.pmu.pmu_pg_init_param, g->ops.pmu.pmu_pg_supported_engines_list, g->ops.pmu.pmu_pg_engines_feature_list, g->ops.pmu.pmu_is_lpwr_feature_supported, g->ops.pmu.pmu_lpwr_enable_pg, g->ops.pmu.pmu_lpwr_disable_pg, g->ops.pmu.pmu_pg_param_post_init, g->ops.pmu.save_zbc Change the function access by using sw ops, like: Create new functions: int nvgpu_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, struct pmu_pg_stats_data *pg_stat_data); void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries); bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id); JIRA NVGPU-3209 Change-Id: I6db9b43c7c4a5054720a72487302b740b091044d Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2110963 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -25,9 +25,10 @@
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static int lpwr_debug_show(struct seq_file *s, void *data)
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{
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struct gk20a *g = s->private;
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struct nvgpu_pmu *pmu = &g->pmu;
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if (g->ops.pmu.pmu_pg_engines_feature_list &&
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g->ops.pmu.pmu_pg_engines_feature_list(g,
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if (pmu->pg->engines_feature_list &&
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pmu->pg->engines_feature_list(g,
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PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
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NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
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seq_printf(s, "PSTATE: %u\n"
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