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gpu: nvgpu: gr/intr MISRA Fix for Rule 21.2

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Fix MISRA Rule 21.2 violations in hal/gr/intr unit
A reserved identifier or macro name shall not be used

Jira NVGPU-3393

Change-Id: Ib43ab15bfe8e54b2848d0fc8ae7cb5424ddf48ff
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114039
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-05-07 13:32:28 -07:00
committed by mobile promotions
parent e2a712441d
commit 8e86bcfdfe
4 changed files with 8 additions and 8 deletions
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8
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c
View File

@@ -68,7 +68,7 @@ static int gp10b_gr_intr_clear_cilp_preempt_pending(struct gk20a *g,
}
static int gp10b_gr_intr_get_cilp_preempt_pending_chid(struct gk20a *g,
u32 *__chid)
u32 *chid_ptr)
{
struct nvgpu_gr_ctx *gr_ctx;
struct nvgpu_channel *ch;
@@ -95,7 +95,7 @@ static int gp10b_gr_intr_get_cilp_preempt_pending_chid(struct gk20a *g,
gr_ctx = tsg->gr_ctx;
if (nvgpu_gr_ctx_get_cilp_preempt_pending(gr_ctx)) {
*__chid = chid;
*chid_ptr = chid;
ret = 0;
}
@@ -105,7 +105,7 @@ static int gp10b_gr_intr_get_cilp_preempt_pending_chid(struct gk20a *g,
}
int gp10b_gr_intr_handle_fecs_error(struct gk20a *g,
struct nvgpu_channel *__ch,
struct nvgpu_channel *ch_ptr,
struct nvgpu_gr_isr_data *isr_data)
{
struct nvgpu_channel *ch;
@@ -169,7 +169,7 @@ int gp10b_gr_intr_handle_fecs_error(struct gk20a *g,
clean_up:
/* handle any remaining interrupts */
return nvgpu_gr_intr_handle_fecs_error(g, __ch, isr_data);
return nvgpu_gr_intr_handle_fecs_error(g, ch_ptr, isr_data);
}
void gp10b_gr_intr_set_go_idle_timeout(struct gk20a *g, u32 data)

2
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.h
View File

@@ -41,7 +41,7 @@ struct nvgpu_gr_isr_data;
#define NVC0C0_SET_RD_COALESCE 0x0228U
int gp10b_gr_intr_handle_fecs_error(struct gk20a *g,
struct nvgpu_channel *__ch,
struct nvgpu_channel *ch_ptr,
struct nvgpu_gr_isr_data *isr_data);
void gp10b_gr_intr_set_coalesce_buffer_size(struct gk20a *g, u32 data);
void gp10b_gr_intr_set_go_idle_timeout(struct gk20a *g, u32 data);

4
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
View File

@@ -84,7 +84,7 @@ static void gv11b_gr_intr_handle_fecs_ecc_error(struct gk20a *g)
}
int gv11b_gr_intr_handle_fecs_error(struct gk20a *g,
struct nvgpu_channel *__ch,
struct nvgpu_channel *ch_ptr,
struct nvgpu_gr_isr_data *isr_data)
{
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, " ");
@@ -92,7 +92,7 @@ int gv11b_gr_intr_handle_fecs_error(struct gk20a *g,
/* Handle ECC errors */
gv11b_gr_intr_handle_fecs_ecc_error(g);
return gp10b_gr_intr_handle_fecs_error(g, __ch, isr_data);
return gp10b_gr_intr_handle_fecs_error(g, ch_ptr, isr_data);
}
void gv11b_gr_intr_set_tex_in_dbg(struct gk20a *g, u32 data)

2
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h
View File

@@ -58,7 +58,7 @@ struct nvgpu_gr_isr_data;
#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE U32(0)
int gv11b_gr_intr_handle_fecs_error(struct gk20a *g,
struct nvgpu_channel *__ch,
struct nvgpu_channel *ch_ptr,
struct nvgpu_gr_isr_data *isr_data);
void gv11b_gr_intr_set_shader_cut_collector(struct gk20a *g, u32 data);
void gv11b_gr_intr_set_skedcheck(struct gk20a *g, u32 data);