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gpu: nvgpu: Use sw ops for PMU PG unit

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Some functions are not accessing hardware directly
but are being called using HAL ops: For example

g->ops.pmu.pmu_elpg_statistics,
g->ops.pmu.pmu_pg_init_param,
g->ops.pmu.pmu_pg_supported_engines_list,
g->ops.pmu.pmu_pg_engines_feature_list,
g->ops.pmu.pmu_is_lpwr_feature_supported,
g->ops.pmu.pmu_lpwr_enable_pg,
g->ops.pmu.pmu_lpwr_disable_pg,
g->ops.pmu.pmu_pg_param_post_init,
g->ops.pmu.save_zbc

Change the function access by using sw ops, like:
Create new functions:

int nvgpu_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
		struct pmu_pg_stats_data *pg_stat_data);
void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries);
bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g,
			u32 feature_id);

JIRA NVGPU-3209

Change-Id: I6db9b43c7c4a5054720a72487302b740b091044d
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110963
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya Singhatwaria
2019-05-02 11:31:41 +05:30
committed by mobile promotions
parent 8e86bcfdfe
commit 5ec94e4a98
19 changed files with 173 additions and 96 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/os/linux/sysfs.c
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@@ -463,6 +463,7 @@ static ssize_t ldiv_slowdown_factor_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct gk20a *g = get_gk20a(dev);
struct nvgpu_pmu *pmu = &g->pmu;
unsigned long val = 0;
int err;
@@ -489,10 +490,9 @@ static ssize_t ldiv_slowdown_factor_store(struct device *dev,
g->ldiv_slowdown_factor = val;
if (g->ops.pmu.pmu_pg_init_param)
g->ops.pmu.pmu_pg_init_param(g,
if (pmu->pg->init_param)
pmu->pg->init_param(g,
PMU_PG_ELPG_ENGINE_ID_GRAPHICS);
gk20a_idle(g);
}
@@ -536,7 +536,7 @@ static ssize_t mscg_enable_store(struct device *dev,
*/
if (val && !g->mscg_enabled) {
g->mscg_enabled = true;
if (g->ops.pmu.pmu_is_lpwr_feature_supported(g,
if (nvgpu_pmu_is_lpwr_feature_supported(g,
PMU_PG_LPWR_FEATURE_MSCG)) {
if (!ACCESS_ONCE(pmu->pg->mscg_stat)) {
WRITE_ONCE(pmu->pg->mscg_stat,
@@ -547,7 +547,7 @@ static ssize_t mscg_enable_store(struct device *dev,
}
} else if (!val && g->mscg_enabled) {
if (g->ops.pmu.pmu_is_lpwr_feature_supported(g,
if (nvgpu_pmu_is_lpwr_feature_supported(g,
PMU_PG_LPWR_FEATURE_MSCG)) {
nvgpu_pmu_pg_global_enable(g, false);
WRITE_ONCE(pmu->pg->mscg_stat, PMU_MSCG_DISABLED);