gpu: nvgpu: Use sw ops for PMU PG unit

Some functions are not accessing hardware directly
but are being called using HAL ops: For example

g->ops.pmu.pmu_elpg_statistics,
g->ops.pmu.pmu_pg_init_param,
g->ops.pmu.pmu_pg_supported_engines_list,
g->ops.pmu.pmu_pg_engines_feature_list,
g->ops.pmu.pmu_is_lpwr_feature_supported,
g->ops.pmu.pmu_lpwr_enable_pg,
g->ops.pmu.pmu_lpwr_disable_pg,
g->ops.pmu.pmu_pg_param_post_init,
g->ops.pmu.save_zbc

Change the function access by using sw ops, like:
Create new functions:

int nvgpu_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
		struct pmu_pg_stats_data *pg_stat_data);
void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries);
bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g,
			u32 feature_id);

JIRA NVGPU-3209

Change-Id: I6db9b43c7c4a5054720a72487302b740b091044d
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110963
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gr/zbc.c

@@ -134,7 +134,7 @@ static int nvgpu_gr_zbc_add(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
 		entries = max(zbc->max_used_color_index,
 					zbc->max_used_depth_index);
 		if (g->elpg_enabled) {
-			g->ops.pmu.save_zbc(g, entries);
+			nvgpu_pmu_save_zbc(g, entries);
 		}
 	}
 

drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gm20b.c

@@ -109,3 +109,17 @@ int gm20b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
 
 	return err;
 }
+
+void nvgpu_gm20b_pg_sw_init(struct gk20a *g,
+		struct nvgpu_pmu_pg *pg)
+{
+	pg->elpg_statistics = gm20b_pmu_elpg_statistics;
+	pg->init_param = NULL;
+	pg->supported_engines_list = gm20b_pmu_pg_engines_list;
+	pg->engines_feature_list = gm20b_pmu_pg_feature_list;
+	pg->is_lpwr_feature_supported = NULL;
+	pg->lpwr_enable_pg = NULL;
+	pg->lpwr_disable_pg = NULL;
+	pg->param_post_init = NULL;
+	pg->save_zbc = gm20b_pmu_save_zbc;
+}

drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gm20b.h

@@ -20,8 +20,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef NVGPU_PG_SW_GM20B_H
+#ifndef NVGPU_PMU_PG_SW_GM20B_H
-#define NVGPU_PG_SW_GM20B_H
+#define NVGPU_PMU_PG_SW_GM20B_H
 
 #include <nvgpu/types.h>
 
@@ -35,5 +35,7 @@ u32 gm20b_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id);
 void gm20b_pmu_save_zbc(struct gk20a *g, u32 entries);
 int gm20b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
 	struct pmu_pg_stats_data *pg_stat_data);
+void nvgpu_gm20b_pg_sw_init(struct gk20a *g,
+		struct nvgpu_pmu_pg *pg);
 
-#endif /* NVGPU_PG_SW_GM20B_H */
+#endif /* NVGPU_PMU_PG_SW_GM20B_H */

drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp10b.c

@@ -27,6 +27,7 @@
 #include <nvgpu/pmu/cmd.h>
 
 #include "pg_sw_gp10b.h"
+#include "pg_sw_gm20b.h"
 
 static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg,
 				void *param, u32 status)
@@ -100,3 +101,13 @@ int gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
 
 	return err;
 }
+
+void nvgpu_gp10b_pg_sw_init(struct gk20a *g,
+		struct nvgpu_pmu_pg *pg)
+{
+	pg->elpg_statistics = gp10b_pmu_elpg_statistics;
+	pg->init_param = gp10b_pg_gr_init;
+	pg->supported_engines_list = gm20b_pmu_pg_engines_list;
+	pg->engines_feature_list = gm20b_pmu_pg_feature_list;
+	pg->save_zbc = gm20b_pmu_save_zbc;
+}

drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gp10b.h

@@ -20,8 +20,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef NVGPU_PG_SW_GP10B_H
+#ifndef NVGPU_PMU_PG_SW_GP10B_H
-#define NVGPU_PG_SW_GP10B_H
+#define NVGPU_PMU_PG_SW_GP10B_H
 
 #include <nvgpu/types.h>
 
@@ -31,5 +31,7 @@ struct pmu_pg_stats_data;
 int gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
 		struct pmu_pg_stats_data *pg_stat_data);
 int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id);
+void nvgpu_gp10b_pg_sw_init(struct gk20a *g,
+		struct nvgpu_pmu_pg *pg);
 
-#endif /* NVGPU_PG_SW_GP10B_H */
+#endif /* NVGPU_PMU_PG_SW_GP10B_H */

drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gv11b.c

@@ -26,6 +26,8 @@
 #include <nvgpu/pmu/cmd.h>
 
 #include "pg_sw_gv11b.h"
+#include "pg_sw_gp106.h"
+#include "pg_sw_gm20b.h"
 
 static void pmu_handle_pg_sub_feature_msg(struct gk20a *g, struct pmu_msg *msg,
 			void *param, u32 status)
@@ -125,3 +127,14 @@ int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id)
 
 	return 0;
 }
+
+void nvgpu_gv11b_pg_sw_init(struct gk20a *g,
+		struct nvgpu_pmu_pg *pg)
+{
+	pg->elpg_statistics = gp106_pmu_elpg_statistics;
+	pg->init_param = gv11b_pg_gr_init;
+	pg->supported_engines_list = gm20b_pmu_pg_engines_list;
+	pg->engines_feature_list = gm20b_pmu_pg_feature_list;
+	pg->set_sub_feature_mask = gv11b_pg_set_subfeature_mask;
+	pg->save_zbc = gm20b_pmu_save_zbc;
+}

drivers/gpu/nvgpu/common/pmu/pg/pg_sw_gv11b.h

@@ -20,8 +20,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef NVGPU_PG_SW_GV11B_H
+#ifndef NVGPU_PMU_PG_SW_GV11B_H
-#define NVGPU_PG_SW_GV11B_H
+#define NVGPU_PMU_PG_SW_GV11B_H
 
 #include <nvgpu/types.h>
 
@@ -29,5 +29,6 @@ struct gk20a;
 
 int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id);
 int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id);
+void nvgpu_gv11b_pg_sw_init(struct gk20a *g, struct nvgpu_pmu_pg *pg);
 
-#endif /* NVGPU_PG_SW_GV11B_H */
+#endif /* NVGPU_PMU_PG_SW_GV11B_H */

drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c

@@ -33,6 +33,10 @@
 #include <nvgpu/dma.h>
 #include <nvgpu/pmu/fw.h>
 
+#include "pg_sw_gm20b.h"
+#include "pg_sw_gv11b.h"
+#include "pg_sw_gp10b.h"
+
 /* state transition :
  * OFF => [OFF_ON_PENDING optional] => ON_PENDING => ON => OFF
  * ON => OFF is always synchronized
@@ -76,7 +80,7 @@ static int pmu_pg_setup_hw_enable_elpg(struct gk20a *g, struct nvgpu_pmu *pmu,
 	if (nvgpu_is_enabled(g, NVGPU_PMU_ZBC_SAVE)) {
 		/* Save zbc table after PMU is initialized. */
 		pg->zbc_ready = true;
-		g->ops.pmu.save_zbc(g, 0xf);
+		nvgpu_pmu_save_zbc(g, 0xf);
 	}
 
 	if (g->elpg_enabled) {
@@ -152,8 +156,8 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg,
 
 		if (nvgpu_pmu_get_fw_state(g, pmu) ==
 			PMU_FW_STATE_ELPG_BOOTING) {
-			if (g->ops.pmu.pmu_pg_engines_feature_list != NULL &&
+			if (pmu->pg->engines_feature_list != NULL &&
-				g->ops.pmu.pmu_pg_engines_feature_list(g,
+				pmu->pg->engines_feature_list(g,
 					PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
 				NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
 				pmu->pg->initialized = true;
@@ -178,31 +182,32 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg,
 /* PG enable/disable */
 int nvgpu_pmu_pg_global_enable(struct gk20a *g, bool enable_pg)
 {
+	struct nvgpu_pmu *pmu = &g->pmu;
 	int status = 0;
 
-	if (!is_pg_supported(g, g->pmu.pg)) {
+	if (!is_pg_supported(g, pmu->pg)) {
 		return status;
 	}
 
 	if (enable_pg) {
-		if (g->ops.pmu.pmu_pg_engines_feature_list != NULL &&
+		if (pmu->pg->engines_feature_list != NULL &&
-			g->ops.pmu.pmu_pg_engines_feature_list(g,
+			pmu->pg->engines_feature_list(g,
 				PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
 			NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
-			if (g->ops.pmu.pmu_lpwr_enable_pg != NULL) {
+			if (pmu->pg->lpwr_enable_pg != NULL) {
-				status = g->ops.pmu.pmu_lpwr_enable_pg(g,
+				status = pmu->pg->lpwr_enable_pg(g,
 						true);
 			}
 		} else if (g->can_elpg) {
 			status = nvgpu_pmu_enable_elpg(g);
 		}
 	} else {
-		if (g->ops.pmu.pmu_pg_engines_feature_list != NULL &&
+		if (pmu->pg->engines_feature_list != NULL &&
-			g->ops.pmu.pmu_pg_engines_feature_list(g,
+			pmu->pg->engines_feature_list(g,
 				PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
 			NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
-			if (g->ops.pmu.pmu_lpwr_disable_pg != NULL) {
+			if (pmu->pg->lpwr_disable_pg != NULL) {
-				status = g->ops.pmu.pmu_lpwr_disable_pg(g,
+				status = pmu->pg->lpwr_disable_pg(g,
 						true);
 			}
 		} else if (g->can_elpg) {
@@ -296,8 +301,8 @@ int nvgpu_pmu_enable_elpg(struct gk20a *g)
 		goto exit_unlock;
 	}
 
-	if (g->ops.pmu.pmu_pg_supported_engines_list != NULL) {
+	if (pmu->pg->supported_engines_list != NULL) {
-		pg_engine_id_list = g->ops.pmu.pmu_pg_supported_engines_list(g);
+		pg_engine_id_list = pmu->pg->supported_engines_list(g);
 	}
 
 	for (pg_engine_id = PMU_PG_ELPG_ENGINE_ID_GRAPHICS;
@@ -354,8 +359,8 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g)
 		return ret;
 	}
 
-	if (g->ops.pmu.pmu_pg_supported_engines_list != NULL) {
+	if (pmu->pg->supported_engines_list != NULL) {
-		pg_engine_id_list = g->ops.pmu.pmu_pg_supported_engines_list(g);
+		pg_engine_id_list = pmu->pg->supported_engines_list(g);
 	}
 
 	nvgpu_mutex_acquire(&pmu->pg->elpg_mutex);
@@ -496,10 +501,10 @@ static int pmu_pg_init_send(struct gk20a *g, u8 pg_engine_id)
 
 	g->ops.pmu.pmu_pg_idle_counter_config(g, pg_engine_id);
 
-	if (g->ops.pmu.pmu_pg_init_param != NULL) {
+	if (pmu->pg->init_param != NULL) {
-		err = g->ops.pmu.pmu_pg_init_param(g, pg_engine_id);
+		err = pmu->pg->init_param(g, pg_engine_id);
 		if (err != 0) {
-			nvgpu_err(g, "pmu_pg_init_param failed err=%d", err);
+			nvgpu_err(g, "init_param failed err=%d", err);
 			return err;
 		}
 	}
@@ -568,8 +573,8 @@ static int pmu_pg_init_send(struct gk20a *g, u8 pg_engine_id)
 		return err;
 	}
 
-	if (g->ops.pmu.pmu_pg_set_sub_feature_mask != NULL) {
+	if (pmu->pg->set_sub_feature_mask != NULL) {
-		err = g->ops.pmu.pmu_pg_set_sub_feature_mask(g, pg_engine_id);
+		err = pmu->pg->set_sub_feature_mask(g, pg_engine_id);
 		if (err != 0) {
 			nvgpu_err(g, "set_sub_feature_mask failed err=%d",
 				err);
@@ -589,8 +594,8 @@ static int pmu_pg_init_powergating(struct gk20a *g, struct nvgpu_pmu *pmu,
 
 	nvgpu_log_fn(g, " ");
 
-	if (g->ops.pmu.pmu_pg_supported_engines_list != NULL) {
+	if (pmu->pg->supported_engines_list != NULL) {
-		pg_engine_id_list = g->ops.pmu.pmu_pg_supported_engines_list(g);
+		pg_engine_id_list = pmu->pg->supported_engines_list(g);
 	}
 
 	g->ops.gr.init.wait_initialized(g);
@@ -614,9 +619,9 @@ static int pmu_pg_init_powergating(struct gk20a *g, struct nvgpu_pmu *pmu,
 		}
 	}
 
-	if (g->ops.pmu.pmu_pg_param_post_init != NULL) {
+	if (pmu->pg->param_post_init != NULL) {
-		/* Error print handled by pmu_pg_param_post_init */
+		/* Error print handled by param_post_init */
-		err = g->ops.pmu.pmu_pg_param_post_init(g);
+		err = pmu->pg->param_post_init(g);
 	}
 
 	return err;
@@ -748,13 +753,12 @@ int nvgpu_pmu_get_pg_stats(struct gk20a *g, u32 pg_engine_id,
 		return 0;
 	}
 
-	if (g->ops.pmu.pmu_pg_supported_engines_list != NULL) {
+	if (pmu->pg->supported_engines_list != NULL) {
-		pg_engine_id_list = g->ops.pmu.pmu_pg_supported_engines_list(g);
+		pg_engine_id_list = pmu->pg->supported_engines_list(g);
 	}
 
 	if ((BIT32(pg_engine_id) & pg_engine_id_list) != 0U) {
-		err = g->ops.pmu.pmu_elpg_statistics(g, pg_engine_id,
+		err = nvgpu_pmu_elpg_statistics(g, pg_engine_id, pg_stat_data);
-			pg_stat_data);
 	}
 
 	return err;
@@ -966,6 +970,7 @@ int nvgpu_pmu_pg_init(struct gk20a *g, struct nvgpu_pmu *pmu,
 {
 	struct nvgpu_pmu_pg *pg;
 	int err = 0;
+	u32 ver = g->params.gpu_arch + g->params.gpu_impl;
 
 	if (*pg_p != NULL) {
 		/* skip alloc/reinit for unrailgate sequence */
@@ -1001,6 +1006,27 @@ int nvgpu_pmu_pg_init(struct gk20a *g, struct nvgpu_pmu *pmu,
 	}
 
 	*pg_p = pg;
+
+	switch (ver) {
+	case GK20A_GPUID_GM20B:
+	case GK20A_GPUID_GM20B_B:
+		nvgpu_gm20b_pg_sw_init(g, *pg_p);
+		break;
+
+	case NVGPU_GPUID_GP10B:
+		nvgpu_gp10b_pg_sw_init(g, *pg_p);
+		break;
+
+	case NVGPU_GPUID_GV11B:
+		nvgpu_gv11b_pg_sw_init(g, *pg_p);
+		break;
+
+	default:
+		nvgpu_kfree(g, *pg_p);
+		err = -EINVAL;
+		nvgpu_err(g, "no support for GPUID %x", ver);
+		break;
+	}
 exit:
 	return err;
 }
@@ -1031,3 +1057,37 @@ void nvgpu_pmu_set_golden_image_initialized(struct gk20a *g, bool initialized)
 
 	pmu->pg->golden_image_initialized = initialized;
 }
+
+int nvgpu_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
+			struct pmu_pg_stats_data *pg_stat_data)
+{
+	struct nvgpu_pmu *pmu = &g->pmu;
+
+	if (!is_pg_supported(g, pmu->pg)) {
+		return 0;
+	}
+
+	return pmu->pg->elpg_statistics(g, pg_engine_id, pg_stat_data);
+}
+
+void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries)
+{
+	struct nvgpu_pmu *pmu = &g->pmu;
+
+	if (!is_pg_supported(g, pmu->pg)) {
+		return;
+	}
+
+	return pmu->pg->save_zbc(g, entries);
+}
+
+bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id)
+{
+	struct nvgpu_pmu *pmu = &g->pmu;
+
+	if (!is_pg_supported(g, pmu->pg)) {
+		return false;
+	}
+
+	return pmu->pg->is_lpwr_feature_supported(g, feature_id);
+}

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -635,14 +635,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.pmu_dump_falcon_stats = NULL,
 		.pmu_enable_irq = NULL,
 		.write_dmatrfbase = NULL,
-		.pmu_elpg_statistics = NULL,
-		.pmu_pg_init_param = NULL,
-		.pmu_pg_supported_engines_list = NULL,
-		.pmu_pg_engines_feature_list = NULL,
 		.dump_secure_fuses = NULL,
 		.reset_engine = NULL,
 		.is_engine_in_reset = NULL,
-		.save_zbc = NULL,
 	},
 	.clk_arb = {
 		.check_clk_arb_support = gp10b_check_clk_arb_support,

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -723,17 +723,11 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.pmu_dump_falcon_stats = NULL,
 		.pmu_enable_irq = NULL,
 		.write_dmatrfbase = NULL,
-		.pmu_elpg_statistics = NULL,
-		.pmu_pg_init_param = NULL,
-		.pmu_pg_supported_engines_list = NULL,
-		.pmu_pg_engines_feature_list = NULL,
 		.dump_secure_fuses = NULL,
 		.reset_engine = NULL,
 		.is_engine_in_reset = NULL,
 		.pmu_ns_bootstrap = NULL,
-		.pmu_pg_set_sub_feature_mask = NULL,
 		.is_pmu_supported = NULL,
-		.save_zbc = NULL,
 	},
 	.clk_arb = {
 		.check_clk_arb_support = gp10b_check_clk_arb_support,

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -798,20 +798,11 @@ static const struct gpu_ops gm20b_ops = {
 		.pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats,
 		.pmu_enable_irq = gk20a_pmu_enable_irq,
 		.write_dmatrfbase = gm20b_write_dmatrfbase,
-		.pmu_elpg_statistics = gm20b_pmu_elpg_statistics,
-		.pmu_pg_init_param = NULL,
-		.pmu_pg_supported_engines_list = gm20b_pmu_pg_engines_list,
-		.pmu_pg_engines_feature_list = gm20b_pmu_pg_feature_list,
-		.pmu_is_lpwr_feature_supported = NULL,
-		.pmu_lpwr_enable_pg = NULL,
-		.pmu_lpwr_disable_pg = NULL,
-		.pmu_pg_param_post_init = NULL,
 		.dump_secure_fuses = pmu_dump_security_fuses_gm20b,
 		.reset_engine = gk20a_pmu_engine_reset,
 		.is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
 		.get_irqdest = gk20a_pmu_get_irqdest,
 		.is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en,
-		.save_zbc = gm20b_pmu_save_zbc,
 		.pmu_clear_bar0_host_err_status =
 			gm20b_clear_pmu_bar0_host_err_status,
 		.bar0_error_status = gk20a_pmu_bar0_error_status,

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -873,16 +873,11 @@ static const struct gpu_ops gp10b_ops = {
 		.pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats,
 		.pmu_enable_irq = gk20a_pmu_enable_irq,
 		.write_dmatrfbase = gp10b_write_dmatrfbase,
-		.pmu_elpg_statistics = gp10b_pmu_elpg_statistics,
-		.pmu_pg_init_param = gp10b_pg_gr_init,
-		.pmu_pg_supported_engines_list = gm20b_pmu_pg_engines_list,
-		.pmu_pg_engines_feature_list = gm20b_pmu_pg_feature_list,
 		.dump_secure_fuses = pmu_dump_security_fuses_gm20b,
 		.reset_engine = gk20a_pmu_engine_reset,
 		.is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
 		.get_irqdest = gk20a_pmu_get_irqdest,
 		.is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en,
-		.save_zbc = gm20b_pmu_save_zbc,
 		.pmu_clear_bar0_host_err_status =
 			gm20b_clear_pmu_bar0_host_err_status,
 		.bar0_error_status = gk20a_pmu_bar0_error_status,

drivers/gpu/nvgpu/hal/init/hal_gv100.c

@@ -1034,7 +1034,6 @@ static const struct gpu_ops gv100_ops = {
 		.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
 		.pmu_reset = nvgpu_pmu_reset,
 		.pmu_queue_head = gk20a_pmu_queue_head,
-		.pmu_pg_param_post_init = nvgpu_lpwr_post_init,
 		.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
 		.reset_engine = gp106_pmu_engine_reset,
 		.write_dmatrfbase = gp10b_write_dmatrfbase,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -1016,13 +1016,8 @@ static const struct gpu_ops gv11b_ops = {
 		.pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
 		.pmu_mutex_release = gk20a_pmu_mutex_release,
 		/* power-gating */
-		.pmu_pg_init_param = gv11b_pg_gr_init,
 		.pmu_setup_elpg = gv11b_pmu_setup_elpg,
 		.pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config,
-		.pmu_pg_supported_engines_list = gm20b_pmu_pg_engines_list,
-		.pmu_pg_engines_feature_list = gm20b_pmu_pg_feature_list,
-		.pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask,
-		.pmu_elpg_statistics = gp106_pmu_elpg_statistics,
 		.pmu_dump_elpg_stats = gk20a_pmu_dump_elpg_stats,
 		/* perfmon */
 		.pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter,
@@ -1033,8 +1028,7 @@ static const struct gpu_ops gv11b_ops = {
 		/* debug */
 		.dump_secure_fuses = pmu_dump_security_fuses_gm20b,
 		.pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats,
-		/* PMU uocde */
+		/* PMU ucode */
-		.save_zbc = gm20b_pmu_save_zbc,
 		.pmu_clear_bar0_host_err_status =
 			gm20b_clear_pmu_bar0_host_err_status,
 		.bar0_error_status = gk20a_pmu_bar0_error_status,

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -1075,7 +1075,6 @@ static const struct gpu_ops tu104_ops = {
 		.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
 		.pmu_reset = nvgpu_pmu_reset,
 		.pmu_queue_head = gk20a_pmu_queue_head,
-		.pmu_pg_param_post_init = nvgpu_lpwr_post_init,
 		.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
 		.reset_engine = gp106_pmu_engine_reset,
 		.write_dmatrfbase = gp10b_write_dmatrfbase,

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1423,21 +1423,6 @@ struct gpu_ops {
 		 * PMU RTOS FW version ops, should move under struct nvgpu_pmu's
 		 * pg/perfmon unit struct ops
 		 */
-		/* pg */
-		int (*pmu_elpg_statistics)(struct gk20a *g, u32 pg_engine_id,
-			struct pmu_pg_stats_data *pg_stat_data);
-		int (*pmu_pg_init_param)(struct gk20a *g, u32 pg_engine_id);
-		int (*pmu_pg_set_sub_feature_mask)(struct gk20a *g,
-			u32 pg_engine_id);
-		u32 (*pmu_pg_supported_engines_list)(struct gk20a *g);
-		u32 (*pmu_pg_engines_feature_list)(struct gk20a *g,
-			u32 pg_engine_id);
-		bool (*pmu_is_lpwr_feature_supported)(struct gk20a *g,
-			u32 feature_id);
-		int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock);
-		int (*pmu_lpwr_disable_pg)(struct gk20a *g, bool pstate_lock);
-		int (*pmu_pg_param_post_init)(struct gk20a *g);
-		void (*save_zbc)(struct gk20a *g, u32 entries);
 	} pmu;
 	struct {
 		int (*init_debugfs)(struct gk20a *g);

drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pg.h

@@ -35,6 +35,7 @@
 
 struct nvgpu_pmu;
 struct vm_gk20a;
+struct pmu_pg_stats_data;
 
 /*PG defines used by nvpgu-pmu*/
 #define PMU_PG_IDLE_THRESHOLD_SIM		1000U
@@ -83,6 +84,20 @@ struct nvgpu_pmu_pg {
 	bool golden_image_initialized;
 	u32 mscg_stat;
 	u32 mscg_transition_state;
+	int (*elpg_statistics)(struct gk20a *g, u32 pg_engine_id,
+		struct pmu_pg_stats_data *pg_stat_data);
+	int (*init_param)(struct gk20a *g, u32 pg_engine_id);
+	int (*set_sub_feature_mask)(struct gk20a *g,
+		u32 pg_engine_id);
+	u32 (*supported_engines_list)(struct gk20a *g);
+	u32 (*engines_feature_list)(struct gk20a *g,
+		u32 pg_engine_id);
+	bool (*is_lpwr_feature_supported)(struct gk20a *g,
+		u32 feature_id);
+	int (*lpwr_enable_pg)(struct gk20a *g, bool pstate_lock);
+	int (*lpwr_disable_pg)(struct gk20a *g, bool pstate_lock);
+	int (*param_post_init)(struct gk20a *g);
+	void (*save_zbc)(struct gk20a *g, u32 entries);
 };
 
 /*PG defines used by nvpgu-pmu*/
@@ -120,4 +135,10 @@ int nvgpu_pmu_ap_send_command(struct gk20a *g,
 
 void nvgpu_pmu_set_golden_image_initialized(struct gk20a *g, bool initialized);
 
+/* PG ops*/
+int nvgpu_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
+		struct pmu_pg_stats_data *pg_stat_data);
+void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries);
+bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id);
+
 #endif /* NVGPU_PMU_PG_H */

drivers/gpu/nvgpu/os/linux/debug_pmu.c

@@ -25,9 +25,10 @@
 static int lpwr_debug_show(struct seq_file *s, void *data)
 {
 	struct gk20a *g = s->private;
+	struct nvgpu_pmu *pmu = &g->pmu;
 
-	if (g->ops.pmu.pmu_pg_engines_feature_list &&
+	if (pmu->pg->engines_feature_list &&
-		g->ops.pmu.pmu_pg_engines_feature_list(g,
+		pmu->pg->engines_feature_list(g,
 		PMU_PG_ELPG_ENGINE_ID_GRAPHICS) !=
 		NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING) {
 		seq_printf(s, "PSTATE: %u\n"

drivers/gpu/nvgpu/os/linux/sysfs.c

@@ -463,6 +463,7 @@ static ssize_t ldiv_slowdown_factor_store(struct device *dev,
 	struct device_attribute *attr, const char *buf, size_t count)
 {
 	struct gk20a *g = get_gk20a(dev);
+	struct nvgpu_pmu *pmu = &g->pmu;
 	unsigned long val = 0;
 	int err;
 
@@ -489,10 +490,9 @@ static ssize_t ldiv_slowdown_factor_store(struct device *dev,
 
 		g->ldiv_slowdown_factor = val;
 
-		if (g->ops.pmu.pmu_pg_init_param)
+		if (pmu->pg->init_param)
-			g->ops.pmu.pmu_pg_init_param(g,
+			pmu->pg->init_param(g,
 				PMU_PG_ELPG_ENGINE_ID_GRAPHICS);
-
 		gk20a_idle(g);
 	}
 
@@ -536,7 +536,7 @@ static ssize_t mscg_enable_store(struct device *dev,
 		 */
 		if (val && !g->mscg_enabled) {
 			g->mscg_enabled = true;
-			if (g->ops.pmu.pmu_is_lpwr_feature_supported(g,
+			if (nvgpu_pmu_is_lpwr_feature_supported(g,
 					PMU_PG_LPWR_FEATURE_MSCG)) {
 				if (!ACCESS_ONCE(pmu->pg->mscg_stat)) {
 					WRITE_ONCE(pmu->pg->mscg_stat,
@@ -547,7 +547,7 @@ static ssize_t mscg_enable_store(struct device *dev,
 			}
 
 		} else if (!val && g->mscg_enabled) {
-			if (g->ops.pmu.pmu_is_lpwr_feature_supported(g,
+			if (nvgpu_pmu_is_lpwr_feature_supported(g,
 					PMU_PG_LPWR_FEATURE_MSCG)) {
 				nvgpu_pmu_pg_global_enable(g, false);
 				WRITE_ONCE(pmu->pg->mscg_stat, PMU_MSCG_DISABLED);