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gpu: nvgpu: Add su_rd_coalesce register field

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Add the surface rd coalesce field in the register that
controls read coalescing.

Bug 200314091

Change-Id: I185ad7e6ef64ecae9369e26d22a7381611ddc693
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1518305
(cherry picked from commit 0dd02e634d)
Reviewed-on: https://git-master.nvidia.com/r/1551738
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Darren Sun <darrens@nvidia.com>
Tested-by: Darren Sun <darrens@nvidia.com>
Reviewed-by: Hayden Du <haydend@nvidia.com>
This commit is contained in:
Alex Waterman
2017-07-13 00:40:31 +01:00
committed by mobile promotions
parent d73cc6808d
commit 5ecd220d32
2 changed files with 16 additions and 0 deletions
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8
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
View File

@@ -2266,6 +2266,14 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void)
{
return 0x1 << 2;
}
static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v)
{
return (v & 0x1) << 4;
}
static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void)
{
return 0x1 << 4;
}
static inline u32 gr_gpccs_falcon_addr_r(void)
{
return 0x0041a0ac;

8
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
View File

@@ -2550,6 +2550,14 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void)
{
return 0x1 << 2;
}
static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v)
{
return (v & 0x1) << 4;
}
static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void)
{
return 0x1 << 4;
}
static inline u32 gr_gpccs_falcon_addr_r(void)
{
return 0x0041a0ac;