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nvgpu: unit: Add new mock register framework

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Many tests used various incarnations of the mock register framework.
This was based on a dump of gv11b registers. Tests that greatly
benefitted from having generally sane register values all rely
heavily on this framework.

However, every test essentially did their own thing. This was not
efficient and has caused a some issues in cleaning up the device and
host code.

Therefore introduce a much leaner and simplified register framework.
All unit tests now automatically get a good subset of the gv11b
registers auto-populated. As part of this also populate the HAL with
a nvgpu_detect_chip() call. Many tests can now _probably_ have all
their HAL init (except dummy HAL stuff) deleted. But this does
require a few fixups here and there to set HALs to NULL where tests
expect HALs to be NULL by default.

Where necessary HALs are cleared with a memset to prevent unwanted
code from executing.

Overall, this imposes a far smaller burden on tests to initialize
their environments.

Something to consider for the future, though, is how to handle
supporting multiple chips in the unit test world.

JIRA NVGPU-5422

Change-Id: Icf1a63f728e9c5671ee0fdb726c235ffbd2843e2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335334
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2020-04-27 16:46:52 -05:00
parent b8f398f6a7
commit 5f0fdf085c
66 changed files with 365 additions and 1519 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
userspace/units/fifo/Makefile
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -23,12 +23,5 @@
OBJS = nvgpu-fifo-common.o nvgpu-fifo-gv11b.o
MODULE = nvgpu-fifo-common
LIB_PATHS += -lmock-iospace
include ../Makefile.units
lib$(MODULE).so: mock-iospace
mock-iospace:
$(MAKE) -C ../mock-iospace/

5
userspace/units/fifo/Makefile.tmk
View File

@@ -1,6 +1,6 @@
################################### tell Emacs this is a -*- makefile-gmake -*-
#
# Copyright (c) 2019 NVIDIA CORPORATION. All Rights Reserved.
# Copyright (c) 2019-2020 NVIDIA CORPORATION. All Rights Reserved.
#
# NVIDIA CORPORATION and its licensors retain all intellectual property
# and proprietary rights in and to this software, related documentation
@@ -17,9 +17,6 @@
NVGPU_UNIT_NAME = nvgpu-fifo-common
NVGPU_UNIT_SRCS = nvgpu-fifo-common.c nvgpu-fifo-gv11b.c
NVGPU_UNIT_INTERFACE_DIRS := \
$(NV_SOURCE)/kernel/nvgpu/userspace/units/mock-iospace
include $(NV_COMPONENT_DIR)/../Makefile.units.common.tmk
# Local Variables:

3
userspace/units/fifo/libnvgpu-fifo-common.export
View File

@@ -1,5 +1,5 @@
#
# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -26,4 +26,3 @@ test_fifo_remove_support
test_fifo_subtest_pruned
test_fifo_flags_str
test_fifo_setup_gv11b_reg_space
test_fifo_cleanup_gv11b_reg_space

7
userspace/units/fifo/nvgpu-fifo-common.c
View File

@@ -171,10 +171,6 @@ int test_fifo_init_support(struct unit_module *m, struct gk20a *g, void *args)
g->ops.mm.init_mm_support(g);
err = nvgpu_fifo_init_support(g);
if (err != 0) {
test_fifo_cleanup_gv11b_reg_space(m, g);
goto fail;
}
/* Do not allocate from vidmem */
nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
@@ -192,8 +188,5 @@ int test_fifo_remove_support(struct unit_module *m,
g->fifo.remove_support(&g->fifo);
}
test_fifo_cleanup_gv11b_reg_space(m, g);
return UNIT_SUCCESS;
}

182
userspace/units/fifo/nvgpu-fifo-gv11b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,23 +20,15 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <stdlib.h>
#include <sys/types.h>
#include <unistd.h>
#include <unit/io.h>
#include <unit/unit.h>
#include <unit/module.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/posix/io.h>
#include <nvgpu/posix/soc_fuse.h>
#include <nvgpu/gk20a.h>
#include "hal/fuse/fuse_gm20b.h"
#include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
#include <gv11b_mock_regs.h>
#include "nvgpu-fifo-gv11b.h"
/*
@@ -84,176 +76,10 @@ static struct nvgpu_posix_io_callbacks test_reg_callbacks = {
.tegra_fuse_readl = tegra_fuse_readl_access_reg_fn,
};
struct test_reg_space {
int idx;
u32 base;
u32 size;
const u32 *data;
void (*init)(u32 *data, u32 size);
};
static void init_reg_space_usermode(u32 *data, u32 size)
{
u32 i;
for (i = 0U; i < size/4U; i++) {
data[i] = 0xbadf1100;
}
}
#define NUM_REG_SPACES 11U
struct test_reg_space reg_spaces[NUM_REG_SPACES] = {
[0] = { /* FUSE */
.idx = gv11b_fuse_reg_idx,
.base = 0x00021000,
.size = 0,
.data = NULL,
},
[1] = { /* MASTER */
.idx = gv11b_master_reg_idx,
.base = 0x00000000,
.size = 0,
.data = NULL,
},
[2] = { /* TOP */
.idx = gv11b_top_reg_idx,
.base = 0x22400,
.size = 0,
.data = NULL,
},
[3] = { /* PBDMA */
.idx = gv11b_pbdma_reg_idx,
.base = 0x00040000,
.size = 0,
.data = NULL,
},
[4] = { /* CCSR */
.idx = gv11b_ccsr_reg_idx,
.base = 0x00800000,
.size = 0,
.data = NULL,
},
[5] = { /* FIFO */
.idx = gv11b_fifo_reg_idx,
.base = 0x2000,
.size = 0,
.data = NULL,
},
[6] = { /* USERMODE */
.base = usermode_cfg0_r(),
.size = 0x10000,
.data = NULL,
.init = init_reg_space_usermode,
},
[7] = { /* CE */
.base = 0x104000,
.size = 0x2000,
.data = NULL,
},
[8] = { /* PBUS */
.base = 0x1000,
.size = 0x1000,
.data = NULL,
},
[9] = { /* HSUB_COMMON */
.base = 0x1fbc00,
.size = 0x400,
.data = NULL,
},
[10] = { /* PFB */
.base = 0x100000,
.size = 0x1000,
.data = NULL,
},
};
static void fifo_io_delete_reg_spaces(struct unit_module *m, struct gk20a *g)
{
u32 i = 0;
for (i = 0; i < NUM_REG_SPACES; i++) {
u32 base = reg_spaces[i].base;
nvgpu_posix_io_delete_reg_space(g, base);
}
}
static int fifo_io_add_reg_spaces(struct unit_module *m, struct gk20a *g)
{
int ret = 0;
u32 i = 0, j = 0;
u32 base, size;
struct nvgpu_posix_io_reg_space *reg_space;
for (i = 0; i < NUM_REG_SPACES; i++) {
base = reg_spaces[i].base;
size = reg_spaces[i].size;
if (size == 0) {
struct mock_iospace iospace = {0};
ret = gv11b_get_mock_iospace(reg_spaces[i].idx,
&iospace);
if (ret != 0) {
unit_err(m, "failed to get reg space for %08x\n",
base);
goto clean_init_reg_space;
}
reg_spaces[i].data = iospace.data;
reg_spaces[i].size = size = iospace.size;
}
if (nvgpu_posix_io_add_reg_space(g, base, size) != 0) {
unit_err(m, "failed to add reg space for %08x\n", base);
ret = -ENOMEM;
goto clean_init_reg_space;
}
reg_space = nvgpu_posix_io_get_reg_space(g, base);
if (reg_space == NULL) {
unit_err(m, "failed to get reg space for %08x\n", base);
ret = -EINVAL;
goto clean_init_reg_space;
} else {
unit_info(m, " IO reg space %08x:%08x\n", base + size -1, base);
}
if (reg_spaces[i].data != NULL) {
memcpy(reg_space->data, reg_spaces[i].data, size);
} else {
if (reg_spaces[i].init != NULL) {
reg_spaces[i].init(reg_space->data, size);
} else {
memset(reg_space->data, 0, size);
}
}
}
return ret;
clean_init_reg_space:
for (j = 0; j < i; j++) {
base = reg_spaces[j].base;
nvgpu_posix_io_delete_reg_space(g, base);
}
return ret;
}
int test_fifo_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
{
/* Create register space */
nvgpu_posix_io_init_reg_space(g);
if (fifo_io_add_reg_spaces(m, g) != 0) {
unit_err(m, "failed to get initialized reg space\n");
return UNIT_FAIL;
}
(void)nvgpu_posix_register_io(g, &test_reg_callbacks);
return 0;
}
void test_fifo_cleanup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
{
fifo_io_delete_reg_spaces(m, g);
}

1
userspace/units/fifo/nvgpu-fifo-gv11b.h
View File

@@ -24,6 +24,5 @@
#define UNIT_NVGPU_FIFO_GV11B_H
int test_fifo_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g);
void test_fifo_cleanup_gv11b_reg_space(struct unit_module *m, struct gk20a *g);
#endif /* UNIT_NVGPU_FIFO_GV11B_H */