gpu: nvgpu: add new get_tpc_exception hal

Add new hal to get_tpc_exception to hal.gr.intr

This hal helps to avoid register read from the
common handle_tpc_exception function. Add a new struct to report the
tpc_exception type back to the common code to handle the exception.

JIRA NVGPU-3016

Change-Id: Ib504ade0b06b85cd38ccf166328784bab072573e
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085387
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -46,6 +46,7 @@
 #include "hal/gr/init/gr_init_gm20b.h"
 #include "hal/gr/init/gr_init_gp10b.h"
 #include "hal/gr/init/gr_init_gv11b.h"
+#include "hal/gr/intr/gr_intr_gm20b.h"
 #include "hal/gr/intr/gr_intr_gv11b.h"
 #include "hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h"
 #include "hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h"
@@ -415,6 +416,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 				gv11b_gr_init_commit_gfxp_wfi_timeout,
 		},
 		.intr = {
+			.get_tpc_exception = gm20b_gr_intr_get_tpc_exception,
 			.handle_tpc_mpc_exception =
 					gv11b_gr_intr_handle_tpc_mpc_exception,
 			.handle_tex_exception = NULL,

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -51,6 +51,7 @@
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/gr/zbc.h>
 #include <nvgpu/gr/gr.h>
+#include <nvgpu/gr/gr_intr.h>
 #include <nvgpu/gr/gr_falcon.h>
 #include <nvgpu/gr/obj_ctx.h>
 #include <nvgpu/gr/zcull.h>
@@ -1968,9 +1969,9 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc,
 		u32 *hww_global_esr)
 {
 	int tmp_ret, ret = 0;
+	struct nvgpu_gr_tpc_exception pending_tpc;
 	u32 offset = nvgpu_gr_gpc_offset(g, gpc) + nvgpu_gr_tpc_offset(g, tpc);
-	u32 tpc_exception = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_r()
-			+ offset);
+	u32 tpc_exception = g->ops.gr.intr.get_tpc_exception(g, offset, &pending_tpc);
 	u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
 
 	nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
@@ -1978,8 +1979,7 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc,
 			gpc, tpc, tpc_exception);
 
 	/* check if an sm exeption is pending */
-	if (gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(tpc_exception) ==
-			gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v()) {
+	if (pending_tpc.sm_exception) {
 		u32 esr_sm_sel, sm;
 
 		nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
@@ -2015,12 +2015,10 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc,
 				gpc, tpc, sm, *hww_global_esr);
 
 		}
-
 	}
 
 	/* check if a tex exception is pending */
-	if (gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(tpc_exception) ==
-			gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v()) {
+	if (pending_tpc.tex_exception) {
 		nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
 				"GPC%d TPC%d: TEX exception pending", gpc, tpc);
 		if (g->ops.gr.intr.handle_tex_exception != NULL) {
@@ -2028,8 +2026,13 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc,
 		}
 	}
 
-	if (g->ops.gr.intr.handle_tpc_mpc_exception != NULL) {
-		g->ops.gr.intr.handle_tpc_mpc_exception(g, gpc, tpc);
+	/* check if a mpc exception is pending */
+	if (pending_tpc.mpc_exception) {
+		nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
+				"GPC%d TPC%d: MPC exception pending", gpc, tpc);
+		if (g->ops.gr.intr.handle_tpc_mpc_exception != NULL) {
+			g->ops.gr.intr.handle_tpc_mpc_exception(g, gpc, tpc);
+		}
 	}
 
 	return ret;

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -477,6 +477,7 @@ static const struct gpu_ops gm20b_ops = {
 			.get_gfxp_rtv_cb_size = NULL,
 		},
 		.intr = {
+			.get_tpc_exception = gm20b_gr_intr_get_tpc_exception,
 			.handle_tex_exception =
 					gm20b_gr_intr_handle_tex_exception,
 			.enable_hww_exceptions =

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -562,6 +562,7 @@ static const struct gpu_ops gp10b_ops = {
 				gp10b_gr_init_commit_cbes_reserve,
 		},
 		.intr = {
+			.get_tpc_exception = gm20b_gr_intr_get_tpc_exception,
 			.handle_tex_exception =
 					gp10b_gr_intr_handle_tex_exception,
 			.enable_hww_exceptions =

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -706,6 +706,7 @@ static const struct gpu_ops gv100_ops = {
 				gv11b_gr_init_commit_gfxp_wfi_timeout,
 		},
 		.intr = {
+			.get_tpc_exception = gm20b_gr_intr_get_tpc_exception,
 			.handle_tpc_mpc_exception =
 					gv11b_gr_intr_handle_tpc_mpc_exception,
 			.handle_tex_exception = NULL,

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -665,6 +665,7 @@ static const struct gpu_ops gv11b_ops = {
 				gv11b_gr_init_commit_gfxp_wfi_timeout,
 		},
 		.intr = {
+			.get_tpc_exception = gm20b_gr_intr_get_tpc_exception,
 			.handle_tpc_mpc_exception =
 					gv11b_gr_intr_handle_tpc_mpc_exception,
 			.handle_tex_exception = NULL,

drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c

@@ -24,11 +24,39 @@
 #include <nvgpu/io.h>
 
 #include <nvgpu/gr/config.h>
+#include <nvgpu/gr/gr.h>
+#include <nvgpu/gr/gr_intr.h>
 
 #include "gr_intr_gm20b.h"
 
 #include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
 
+u32 gm20b_gr_intr_get_tpc_exception(struct gk20a *g, u32 offset,
+				    struct nvgpu_gr_tpc_exception *pending_tpc)
+{
+	u32 tpc_exception = nvgpu_readl(g,
+				gr_gpc0_tpc0_tpccs_tpc_exception_r()
+				+ offset);
+
+	(void) memset(pending_tpc, 0, sizeof(struct nvgpu_gr_tpc_exception));
+
+	if (gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(tpc_exception) ==
+		gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v()) {
+			pending_tpc->tex_exception = true;
+	}
+
+	if (gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(tpc_exception) ==
+		gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v()) {
+			pending_tpc->sm_exception = true;
+	}
+
+	if ((tpc_exception & gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m()) != 0U) {
+		pending_tpc->mpc_exception = true;
+	}
+
+	return tpc_exception;
+}
+
 void gm20b_gr_intr_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc)
 {
 	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);

drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.h

@@ -27,7 +27,10 @@
 
 struct gk20a;
 struct nvgpu_gr_config;
+struct nvgpu_gr_tpc_exception;
 
+u32 gm20b_gr_intr_get_tpc_exception(struct gk20a *g, u32 offset,
+			struct nvgpu_gr_tpc_exception *pending_tpc);
 void gm20b_gr_intr_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc);
 void gm20b_gr_intr_enable_hww_exceptions(struct gk20a *g);
 void gm20b_gr_intr_enable_interrupts(struct gk20a *g, bool enable);

drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c

@@ -35,15 +35,6 @@ void gv11b_gr_intr_handle_tpc_mpc_exception(struct gk20a *g, u32 gpc, u32 tpc)
 {
 	u32 esr;
 	u32 offset = nvgpu_gr_gpc_offset(g, gpc) + nvgpu_gr_tpc_offset(g, tpc);
-	u32 tpc_exception = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_r()
-			+ offset);
-
-	if ((tpc_exception & gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m()) == 0U) {
-		return;
-	}
-
-	nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
-			"GPC%d TPC%d MPC exception", gpc, tpc);
 
 	esr = nvgpu_readl(g, gr_gpc0_tpc0_mpc_hww_esr_r() + offset);
 	nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, "mpc hww esr 0x%08x", esr);

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -69,6 +69,7 @@ struct nvgpu_gr_zbc;
 struct nvgpu_gr_zbc_entry;
 struct nvgpu_gr_zbc_query_params;
 struct nvgpu_gr_zcull_info;
+struct nvgpu_gr_tpc_exception;
 struct nvgpu_channel_hw_state;
 struct nvgpu_engine_status_info;
 struct nvgpu_pbdma_status_info;
@@ -781,6 +782,8 @@ struct gpu_ops {
 		} init;
 
 		struct {
+			u32 (*get_tpc_exception)(struct gk20a *g, u32 offset,
+				struct nvgpu_gr_tpc_exception *pending_tpc);
 			void (*handle_tpc_mpc_exception)(struct gk20a *g,
 							u32 gpc, u32 tpc);
 			void (*handle_tex_exception)(struct gk20a *g,

drivers/gpu/nvgpu/include/nvgpu/gr/gr_intr.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GR_INTR_H
+#define NVGPU_GR_INTR_H
+
+#include <nvgpu/types.h>
+
+struct nvgpu_gr_tpc_exception {
+	bool tex_exception;
+	bool sm_exception;
+	bool mpc_exception;
+};
+
+#endif /* NVGPU_GR_INTR_H */

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h

@@ -3250,6 +3250,14 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
 {
 	return 0x00000001U;
 }
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void)
+{
+	return U32(0x1U) << 4U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void)
+{
+	return 0x10U;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
 {
 	return 0x00504610U;

drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h

@@ -3614,6 +3614,14 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
 {
 	return 0x00000001U;
 }
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void)
+{
+	return U32(0x1U) << 4U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void)
+{
+	return 0x10U;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
 {
 	return 0x00504610U;

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -739,6 +739,7 @@ static const struct gpu_ops tu104_ops = {
 				gv11b_gr_init_commit_gfxp_wfi_timeout,
 		},
 		.intr = {
+			.get_tpc_exception = gm20b_gr_intr_get_tpc_exception,
 			.handle_tpc_mpc_exception =
 					gv11b_gr_intr_handle_tpc_mpc_exception,
 			.handle_tex_exception = NULL,