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gpu: nvgpu: Deleting SEC2 HAL's gp106 support

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-Deleting GP106 from SEC2 HAL as GP106 is not supported
 anymore.

JIRA NVGPU-3243

Change-Id: I4cce6169104d18096ff24fa9e4044d5697ad8e8f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168202
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2019-08-05 14:57:09 +05:30
committed by mobile promotions
parent 6f5417680d
commit 5f8fb9f41a
5 changed files with 1 additions and 148 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/nvgpu-hal-new.yaml
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@@ -668,9 +668,7 @@ sec2:
safe: yes
owner: Sagar K
gpu: dgpu
sources: [ hal/sec2/sec2_gp106.c,
hal/sec2/sec2_gp106.h,
hal/sec2/sec2_tu104.c,
sources: [ hal/sec2/sec2_tu104.c,
hal/sec2/sec2_tu104.h ]
netlist_fusa:

1
drivers/gpu/nvgpu/Makefile
View File

@@ -287,7 +287,6 @@ nvgpu-y += \
hal/nvlink/link_mode_transitions_gv100.o \
hal/nvlink/link_mode_transitions_tu104.o \
hal/gsp/gsp_gv100.o \
hal/sec2/sec2_gp106.o \
hal/sec2/sec2_tu104.o \
hal/sync/sema_cmdbuf_gk20a.o \
hal/sync/sema_cmdbuf_gv11b.o \

1
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -615,7 +615,6 @@ srcs += common/sec2/sec2.c \
hal/nvdec/nvdec_gp106.c \
hal/nvdec/nvdec_tu104.c \
hal/gsp/gsp_gv100.c \
hal/sec2/sec2_gp106.c \
hal/sec2/sec2_tu104.c \
hal/pramin/pramin_gp10b.c \
hal/pramin/pramin_gv100.c \

111
drivers/gpu/nvgpu/hal/sec2/sec2_gp106.c
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@@ -1,111 +0,0 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/pmu.h>
#include <nvgpu/falcon.h>
#include <nvgpu/mm.h>
#include <nvgpu/io.h>
#include <nvgpu/timers.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include "sec2_gp106.h"
#include <nvgpu/hw/gp106/hw_pwr_gp106.h>
#include <nvgpu/hw/gp106/hw_psec_gp106.h>
int gp106_sec2_reset(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
gk20a_writel(g, psec_falcon_engine_r(),
pwr_falcon_engine_reset_true_f());
nvgpu_udelay(10);
gk20a_writel(g, psec_falcon_engine_r(),
pwr_falcon_engine_reset_false_f());
nvgpu_log_fn(g, "done");
return 0;
}
void gp106_sec2_flcn_setup_boot_config(struct gk20a *g)
{
struct mm_gk20a *mm = &g->mm;
u32 inst_block_ptr;
u32 data = 0U;
nvgpu_log_fn(g, " ");
data = gk20a_readl(g, psec_fbif_ctl_r());
data |= psec_fbif_ctl_allow_phys_no_ctx_allow_f();
gk20a_writel(g, psec_fbif_ctl_r(), data);
/* setup apertures - virtual */
gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
psec_fbif_transcfg_mem_type_physical_f() |
psec_fbif_transcfg_target_local_fb_f());
gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
psec_fbif_transcfg_mem_type_virtual_f());
/* setup apertures - physical */
gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
psec_fbif_transcfg_mem_type_physical_f() |
psec_fbif_transcfg_target_local_fb_f());
gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
psec_fbif_transcfg_mem_type_physical_f() |
psec_fbif_transcfg_target_coherent_sysmem_f());
gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
psec_fbif_transcfg_mem_type_physical_f() |
psec_fbif_transcfg_target_noncoherent_sysmem_f());
/* enable the context interface */
gk20a_writel(g, psec_falcon_itfen_r(),
gk20a_readl(g, psec_falcon_itfen_r()) |
psec_falcon_itfen_ctxen_enable_f());
/*
* The instance block address to write is the lower 32-bits of the 4K-
* aligned physical instance block address.
*/
inst_block_ptr = nvgpu_inst_block_ptr(g, &mm->sec2.inst_block);
gk20a_writel(g, psec_falcon_nxtctx_r(),
pwr_pmu_new_instblk_ptr_f(inst_block_ptr) |
pwr_pmu_new_instblk_valid_f(1U) |
nvgpu_aperture_mask(g, &mm->sec2.inst_block,
pwr_pmu_new_instblk_target_sys_ncoh_f(),
pwr_pmu_new_instblk_target_sys_coh_f(),
pwr_pmu_new_instblk_target_fb_f()));
data = gk20a_readl(g, psec_falcon_debug1_r());
data |= psec_falcon_debug1_ctxsw_mode_m();
gk20a_writel(g, psec_falcon_debug1_r(), data);
/* Trigger context switch */
data = gk20a_readl(g, psec_falcon_engctl_r());
data |= BIT32(3);
gk20a_writel(g, psec_falcon_engctl_r(), data);
}
u32 gp106_sec2_falcon_base_addr(void)
{
return psec_falcon_irqsset_r();
}

32
drivers/gpu/nvgpu/hal/sec2/sec2_gp106.h
View File

@@ -1,32 +0,0 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_SEC2_GP106_H
#define NVGPU_SEC2_GP106_H
int gp106_sec2_reset(struct gk20a *g);
void gp106_sec2_flcn_setup_boot_config(struct gk20a *g);
u32 gp106_sec2_falcon_base_addr(void);
#endif /* NVGPU_SEC2_GP106_H */