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gpu: nvgpu: Regenerated headers

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Regenerating header from register generator

Bug 2833620

Change-Id: Idc8e922bb611ed5acae66b6ca38db4bb9c8a1904
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335263
(cherry picked from commit dfab7cc86a)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2351900
GVS: Gerrit_Virtual_Submit
Tested-by: Amulya Yarlagadda <ayarlagadda@nvidia.com>
Reviewed-by: Amulya Yarlagadda <ayarlagadda@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
This commit is contained in:
David Ung
2020-04-27 16:15:59 -07:00
committed by Amulya Yarlagadda
parent 053d0a416e
commit 5f9cd1bca5
10 changed files with 34 additions and 22 deletions
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4
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2012-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -706,7 +706,7 @@ static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v)
} }
static inline u32 pwr_pmu_idle_intr_status_intr_m(void) static inline u32 pwr_pmu_idle_intr_status_intr_m(void)
{ {
return U32(0x1U) << 0U; return 0x1U << 0U;
} }
static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r)
{ {

6
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -116,6 +116,10 @@ static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
{ {
return 0x7U << 0U; return 0x7U << 0U;
} }
static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void)
{
return 0x1U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
{ {
return 0x0U; return 0x0U;

4
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -750,7 +750,7 @@ static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v)
} }
static inline u32 pwr_pmu_idle_intr_status_intr_m(void) static inline u32 pwr_pmu_idle_intr_status_intr_m(void)
{ {
return U32(0x1U) << 0U; return 0x1U << 0U;
} }
static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r)
{ {

6
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -104,6 +104,10 @@ static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
{ {
return 0x7U << 0U; return 0x7U << 0U;
} }
static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void)
{
return 0x1U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
{ {
return 0x0U; return 0x0U;

8
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -86,7 +86,7 @@ static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
} }
static inline u32 gmmu_new_pde_address_sys_f(u32 v) static inline u32 gmmu_new_pde_address_sys_f(u32 v)
{ {
return (v & 0xfffffffU) << 8U; return (v & 0xffffffU) << 8U;
} }
static inline u32 gmmu_new_pde_address_sys_w(void) static inline u32 gmmu_new_pde_address_sys_w(void)
{ {
@@ -194,7 +194,7 @@ static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
} }
static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
{ {
return (v & 0xfffffffU) << 8U; return (v & 0xffffffU) << 8U;
} }
static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
{ {
@@ -242,7 +242,7 @@ static inline u32 gmmu_new_pte_privilege_false_f(void)
} }
static inline u32 gmmu_new_pte_address_sys_f(u32 v) static inline u32 gmmu_new_pte_address_sys_f(u32 v)
{ {
return (v & 0xfffffffU) << 8U; return (v & 0xffffffU) << 8U;
} }
static inline u32 gmmu_new_pte_address_sys_w(void) static inline u32 gmmu_new_pte_address_sys_w(void)
{ {

4
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -754,7 +754,7 @@ static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v)
} }
static inline u32 pwr_pmu_idle_intr_status_intr_m(void) static inline u32 pwr_pmu_idle_intr_status_intr_m(void)
{ {
return U32(0x1U) << 0U; return 0x1U << 0U;
} }
static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r)
{ {

6
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -140,6 +140,10 @@ static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
{ {
return 0x7U << 0U; return 0x7U << 0U;
} }
static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void)
{
return 0x1U;
}
static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
{ {
return 0x0U; return 0x0U;

10
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
View File

@@ -62,7 +62,7 @@ static inline u32 fb_fbhub_num_active_ltcs_r(void)
} }
static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void) static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void)
{ {
return U32(0x1U) << 25U; return 0x1U << 25U;
} }
static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void)
{ {
@@ -70,7 +70,7 @@ static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void)
} }
static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m(void) static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m(void)
{ {
return U32(0x1U) << 26U; return 0x1U << 26U;
} }
static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f(void) static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f(void)
{ {
@@ -94,7 +94,7 @@ static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
} }
static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void) static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void)
{ {
return U32(0x3U) << 24U; return 0x3U << 24U;
} }
static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void) static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void)
{ {
@@ -106,7 +106,7 @@ static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void)
} }
static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void) static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void)
{ {
return U32(0x1U) << 27U; return 0x1U << 27U;
} }
static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f(void) static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f(void)
{ {
@@ -118,7 +118,7 @@ static inline u32 fb_hshub_num_active_ltcs_r(void)
} }
static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void) static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void)
{ {
return U32(0x1U) << 25U; return 0x1U << 25U;
} }
static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void)
{ {

4
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
View File

@@ -4978,11 +4978,11 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
} }
static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void) static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void)
{ {
return U32(0x3U) << 24U; return 0x3U << 24U;
} }
static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void) static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void)
{ {
return U32(0x1U) << 27U; return 0x1U << 27U;
} }
static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
{ {

4
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -914,7 +914,7 @@ static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v)
} }
static inline u32 pwr_pmu_idle_intr_status_intr_m(void) static inline u32 pwr_pmu_idle_intr_status_intr_m(void)
{ {
return U32(0x1U) << 0U; return 0x1U << 0U;
} }
static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r)
{ {