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gpu: nvgpu: gk20a: fix MISRA 10.3 violations

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MISRA 10.3 prohibits assignment from an object of different essential or
narrower type. This fixes a number of MISRA 10.3 violations in
gr_gk20a.c in constant values.

JIRA NVGPU-1008

Change-Id: I93eeabe4ab0217a8043a2a025a42d5b95e177bc3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990388
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-01-08 12:32:03 -05:00
committed by mobile promotions
parent edd5a73bbf
commit 60ef4d2e3b
1 changed files with 9 additions and 9 deletions
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18
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -249,15 +249,15 @@ int gr_gk20a_wait_idle(struct gk20a *g)
engine_status = gk20a_readl(g,
fifo_engine_status_r(gr_engine_id));
ctxsw_active = engine_status &
fifo_engine_status_ctxsw_in_progress_f();
ctxsw_active = (engine_status &
fifo_engine_status_ctxsw_in_progress_f()) != 0U;
ctx_status_invalid =
(fifo_engine_status_ctx_status_v(engine_status) ==
fifo_engine_status_ctx_status_invalid_v());
gr_busy = gk20a_readl(g, gr_engine_status_r()) &
gr_engine_status_value_busy_f();
gr_busy = (gk20a_readl(g, gr_engine_status_r()) &
gr_engine_status_value_busy_f()) != 0U;
if (ctx_status_invalid || (!gr_busy && !ctxsw_active)) {
nvgpu_log_fn(g, "done");
@@ -2745,7 +2745,7 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
gr->pes_tpc_count[1][gpc_index] == 5U) {
pes_heavy_index =
gr->pes_tpc_count[0][gpc_index] >
gr->pes_tpc_count[1][gpc_index] ? 0 : 1;
gr->pes_tpc_count[1][gpc_index] ? 0U : 1U;
gpc_new_skip_mask =
gr->pes_tpc_mask[pes_heavy_index][gpc_index] ^
@@ -2759,7 +2759,7 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
gr->pes_tpc_count[1][gpc_index])) {
pes_heavy_index =
gr->pes_tpc_count[0][gpc_index] >
gr->pes_tpc_count[1][gpc_index] ? 0 : 1;
gr->pes_tpc_count[1][gpc_index] ? 0U : 1U;
gpc_new_skip_mask =
gr->pes_tpc_mask[pes_heavy_index][gpc_index] ^
@@ -4934,7 +4934,7 @@ static struct channel_gk20a *gk20a_gr_get_channel_from_ctx(
{
struct fifo_gk20a *f = &g->fifo;
struct gr_gk20a *gr = &g->gr;
u32 chid = -1;
u32 chid;
u32 tsgid = NVGPU_INVALID_TSG_ID;
u32 i;
struct channel_gk20a *ret = NULL;
@@ -6013,7 +6013,7 @@ int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g,
priv_registers = nvgpu_kzalloc(g, sizeof(u32) * potential_offsets);
if (priv_registers == NULL) {
nvgpu_log_fn(g, "failed alloc for potential_offsets=%d", potential_offsets);
err = PTR_ERR(priv_registers);
err = -ENOMEM;
goto cleanup;
}
(void) memset(offsets, 0, sizeof(u32) * max_offsets);
@@ -7375,7 +7375,7 @@ bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch)
* valid context is currently resident.
*/
if (gr_fecs_current_ctx_valid_v(curr_gr_ctx) == 0U) {
return NULL;
return false;
}
curr_ch = gk20a_gr_get_channel_from_ctx(g, curr_gr_ctx,