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gpu: nvgpu: add TSG timeslice support
Add support for changing a TSG's timeslice, within reasonable limits imposed by the kernel driver. JIRA VFND-1494 Bug 1749744 Change-Id: Ifca1b63a00da7a5872483bb56692da70a5f18bdf Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/1129837 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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committed by
Terje Bergstrom
parent
2db5e4794e
commit
610a523b7d
@@ -25,6 +25,9 @@
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#include "gk20a.h"
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#include "hw_ccsr_gk20a.h"
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#define NVGPU_TSG_MIN_TIMESLICE_US 1000
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#define NVGPU_TSG_MAX_TIMESLICE_US 50000
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static void gk20a_tsg_release(struct kref *ref);
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bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch)
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@@ -345,6 +348,20 @@ static int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level)
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return ret ? ret : g->ops.fifo.update_runlist(g, 0, ~0, true, true);
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}
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static int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
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{
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struct gk20a *g = tsg->g;
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if (timeslice < NVGPU_TSG_MIN_TIMESLICE_US ||
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timeslice > NVGPU_TSG_MAX_TIMESLICE_US)
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return -EINVAL;
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gk20a_channel_get_timescale_from_timeslice(g, timeslice,
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&tsg->timeslice_timeout, &tsg->timeslice_scale);
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return g->ops.fifo.update_runlist(g, 0, ~0, true, true);
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}
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static void release_used_tsg(struct fifo_gk20a *f, struct tsg_gk20a *tsg)
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{
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mutex_lock(&f->tsg_inuse_mutex);
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@@ -554,6 +571,20 @@ long gk20a_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
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break;
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}
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case NVGPU_IOCTL_TSG_SET_TIMESLICE:
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{
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err = gk20a_busy(g->dev);
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if (err) {
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gk20a_err(dev_from_gk20a(g),
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"failed to host gk20a for ioctl cmd: 0x%x", cmd);
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return err;
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}
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err = gk20a_tsg_set_timeslice(tsg,
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((struct nvgpu_timeslice_args *)buf)->timeslice_us);
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gk20a_idle(g->dev);
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break;
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}
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default:
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gk20a_err(dev_from_gk20a(g),
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"unrecognized tsg gpu ioctl cmd: 0x%x",
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@@ -467,11 +467,13 @@ struct nvgpu_gpu_get_gpu_time_args {
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_IOWR(NVGPU_TSG_IOCTL_MAGIC, 7, struct nvgpu_event_id_ctrl_args)
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#define NVGPU_IOCTL_TSG_SET_RUNLIST_INTERLEAVE \
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_IOW(NVGPU_TSG_IOCTL_MAGIC, 8, struct nvgpu_runlist_interleave_args)
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#define NVGPU_IOCTL_TSG_SET_TIMESLICE \
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_IOW(NVGPU_TSG_IOCTL_MAGIC, 9, struct nvgpu_timeslice_args)
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#define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \
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sizeof(struct nvgpu_event_id_ctrl_args)
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#define NVGPU_TSG_IOCTL_LAST \
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_IOC_NR(NVGPU_IOCTL_TSG_SET_RUNLIST_INTERLEAVE)
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_IOC_NR(NVGPU_IOCTL_TSG_SET_TIMESLICE)
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/*
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