nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 02:22:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: remove reversed ordering for deadlock

Browse Source 
In some cases, we would get deadlock issue due to there are two locks
acquisition on common clk driver's lock and nvgpu driver's locks. At
the bug, inconsistent lock ordering problem will come with one thread
gets "nvgpu lock -> clk lock" and the other thread gets "clk lock ->
nvgpu lock".

Slove the latter path with one-time initializing clk_parent entry
and use cached data afterward.

Bug 2555115

Change-Id: I31c5c2728f406307e7cfd4e555f4db0c163234d8
Signed-off-by: Jeremy Ho <jeremyh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146727
(cherry picked from commit 42c2bdfb9f)
Reviewed-on: https://git-master.nvidia.com/r/2160290
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Jeremy Ho
2019-07-02 16:43:17 +08:00
committed by Alex Waterman
parent bd2334d79d
commit 6118009b84
3 changed files with 14 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/os/linux/clk.c
View File

@@ -91,7 +91,7 @@ static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct gk20a *g)
*/
if (g->clk.tegra_clk)
return tegra_dvfs_get_fmax_at_vmin_safe_t(
clk_get_parent(g->clk.tegra_clk));
g->clk.tegra_clk_parent);
if (platform->maxmin_clk_id)
return tegra_bpmp_dvfs_get_fmax_at_vmin(
@@ -117,7 +117,7 @@ static int nvgpu_linux_predict_mv_at_hz_cur_tfloor(struct clk_gk20a *clk,
unsigned long rate)
{
return tegra_dvfs_predict_mv_at_hz_cur_tfloor(
clk_get_parent(clk->tegra_clk), rate);
clk->tegra_clk_parent, rate);
}
static unsigned long nvgpu_linux_get_maxrate(struct gk20a *g, u32 api_domain)
@@ -126,7 +126,7 @@ static unsigned long nvgpu_linux_get_maxrate(struct gk20a *g, u32 api_domain)
switch (api_domain) {
case CTRL_CLK_DOMAIN_GPCCLK:
ret = tegra_dvfs_get_maxrate(clk_get_parent(g->clk.tegra_clk));
ret = tegra_dvfs_get_maxrate(g->clk.tegra_clk_parent);
break;
default:
nvgpu_err(g, "unknown clock: %u", api_domain);