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gpu: nvgpu: falcon engine EMEM support

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-Added HAL copy_from_emem & copy_to_emem to struct
nvgpu_falcon_engine_dependency_ops data struct to point to
engine specific EMEM access functions.
-Added function nvgpu_flcn_copy_from_emem() &
 nvgpu_flcn_copy_to_emem() at interface layer to
 access EMEM using flacon engine EMEM HAL's.

JIRA NVGPU-1161

Change-Id: Ifb72a617277e73f25f1772c969791b642585e7fb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807336
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2018-09-23 14:26:26 +05:30
committed by mobile promotions
parent 850f2ad8ad
commit 628e2c7901
2 changed files with 36 additions and 0 deletions
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28
drivers/gpu/nvgpu/common/falcon/falcon.c
View File

@@ -219,6 +219,34 @@ bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn)
return status;
}
int nvgpu_flcn_copy_from_emem(struct nvgpu_falcon *flcn,
u32 src, u8 *dst, u32 size, u8 port)
{
struct nvgpu_falcon_engine_dependency_ops *flcn_dops =
&flcn->flcn_engine_dep_ops;
int status = -EINVAL;
if (flcn_dops->copy_from_emem != NULL) {
status = flcn_dops->copy_from_emem(flcn, src, dst, size, port);
}
return status;
}
int nvgpu_flcn_copy_to_emem(struct nvgpu_falcon *flcn,
u32 dst, u8 *src, u32 size, u8 port)
{
struct nvgpu_falcon_engine_dependency_ops *flcn_dops =
&flcn->flcn_engine_dep_ops;
int status = -EINVAL;
if (flcn_dops->copy_to_emem != NULL) {
status = flcn_dops->copy_to_emem(flcn, dst, src, size, port);
}
return status;
}
int nvgpu_flcn_copy_from_dmem(struct nvgpu_falcon *flcn,
u32 src, u8 *dst, u32 size, u8 port)
{

8
drivers/gpu/nvgpu/include/nvgpu/falcon.h
View File

@@ -219,6 +219,10 @@ struct nvgpu_falcon_engine_dependency_ops {
int (*queue_tail)(struct gk20a *g, struct nvgpu_falcon_queue *queue,
u32 *tail, bool set);
void (*msgq_tail)(struct gk20a *g, u32 *tail, bool set);
int (*copy_from_emem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
u32 size, u8 port);
int (*copy_to_emem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
u32 size, u8 port);
};
struct nvgpu_falcon_ops {
@@ -283,6 +287,10 @@ bool nvgpu_flcn_get_mem_scrubbing_status(struct nvgpu_falcon *flcn);
int nvgpu_flcn_mem_scrub_wait(struct nvgpu_falcon *flcn);
bool nvgpu_flcn_get_cpu_halted_status(struct nvgpu_falcon *flcn);
bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn);
int nvgpu_flcn_copy_from_emem(struct nvgpu_falcon *flcn,
u32 src, u8 *dst, u32 size, u8 port);
int nvgpu_flcn_copy_to_emem(struct nvgpu_falcon *flcn,
u32 dst, u8 *src, u32 size, u8 port);
int nvgpu_flcn_copy_from_dmem(struct nvgpu_falcon *flcn,
u32 src, u8 *dst, u32 size, u8 port);
int nvgpu_flcn_copy_to_dmem(struct nvgpu_falcon *flcn,