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gpu: nvgpu: compile out priv_access_map config/addr hals

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These hals are non-safe. Compile them out with
CONFIG_NVGPU_SET_FALCON_ACCESS_MAP.

JIRA NVGPU-5358

Change-Id: I75b46e201fa132e09fee15679a402d24bbf9b2ab
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2581360
(cherry picked from commit d048333ef391019b2618abf7d09c8fe2042f8ee0)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2581841
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2021-08-23 14:06:49 +05:30
committed by mobile promotions
parent fe7368f8f4
commit 62b04331de
15 changed files with 49 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/gr/ctx.c
View File

@@ -497,12 +497,14 @@ void nvgpu_gr_ctx_load_golden_ctx_image(struct gk20a *g,
}
#endif
#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
/* set priv access map */
g->ops.gr.ctxsw_prog.set_priv_access_map_config_mode(g, mem,
g->allow_all);
g->ops.gr.ctxsw_prog.set_priv_access_map_addr(g, mem,
nvgpu_gr_ctx_get_global_ctx_va(gr_ctx,
NVGPU_GR_CTX_PRIV_ACCESS_MAP_VA));
#endif
/* disable verif features */
g->ops.gr.ctxsw_prog.disable_verif_features(g, mem);

2
drivers/gpu/nvgpu/common/gr/subctx.c
View File

@@ -93,10 +93,12 @@ void nvgpu_gr_subctx_load_ctx_header(struct gk20a *g,
nvgpu_err(g, "l2_flush failed");
}
#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
/* set priv access map */
g->ops.gr.ctxsw_prog.set_priv_access_map_addr(g, ctxheader,
nvgpu_gr_ctx_get_global_ctx_va(gr_ctx,
NVGPU_GR_CTX_PRIV_ACCESS_MAP_VA));
#endif
g->ops.gr.ctxsw_prog.set_patch_addr(g, ctxheader,
nvgpu_gr_ctx_get_patch_ctx_mem(gr_ctx)->gpu_va);

25
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c
View File

@@ -37,6 +37,31 @@ void gm20b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g,
ctxsw_prog_main_image_preemption_options_control_cta_enabled_f());
}
void gm20b_ctxsw_prog_set_config_mode_priv_access_map(struct gk20a *g,
struct nvgpu_mem *ctx_mem, bool allow_all)
{
if (allow_all) {
nvgpu_mem_wr(g, ctx_mem,
ctxsw_prog_main_image_priv_access_map_config_o(),
ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f());
} else {
nvgpu_mem_wr(g, ctx_mem,
ctxsw_prog_main_image_priv_access_map_config_o(),
ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f());
}
}
void gm20b_ctxsw_prog_set_addr_priv_access_map(struct gk20a *g,
struct nvgpu_mem *ctx_mem, u64 addr)
{
nvgpu_mem_wr(g, ctx_mem,
ctxsw_prog_main_image_priv_access_map_addr_lo_o(),
u64_lo32(addr));
nvgpu_mem_wr(g, ctx_mem,
ctxsw_prog_main_image_priv_access_map_addr_hi_o(),
u64_hi32(addr));
}
#ifdef CONFIG_NVGPU_FECS_TRACE
u32 gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp(void)
{

2
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h
View File

@@ -36,10 +36,12 @@ void gm20b_ctxsw_prog_set_patch_addr(struct gk20a *g,
struct nvgpu_mem *ctx_mem, u64 addr);
void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g,
struct nvgpu_mem *ctx_mem);
#if defined(CONFIG_NVGPU_SET_FALCON_ACCESS_MAP)
void gm20b_ctxsw_prog_set_config_mode_priv_access_map(struct gk20a *g,
struct nvgpu_mem *ctx_mem, bool allow_all);
void gm20b_ctxsw_prog_set_addr_priv_access_map(struct gk20a *g,
struct nvgpu_mem *ctx_mem, u64 addr);
#endif
void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g,
struct nvgpu_mem *ctx_mem);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA)

25
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c
View File

@@ -63,31 +63,6 @@ void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g,
ctxsw_prog_main_image_num_restore_ops_o(), 0);
}
void gm20b_ctxsw_prog_set_config_mode_priv_access_map(struct gk20a *g,
struct nvgpu_mem *ctx_mem, bool allow_all)
{
if (allow_all) {
nvgpu_mem_wr(g, ctx_mem,
ctxsw_prog_main_image_priv_access_map_config_o(),
ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f());
} else {
nvgpu_mem_wr(g, ctx_mem,
ctxsw_prog_main_image_priv_access_map_config_o(),
ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f());
}
}
void gm20b_ctxsw_prog_set_addr_priv_access_map(struct gk20a *g,
struct nvgpu_mem *ctx_mem, u64 addr)
{
nvgpu_mem_wr(g, ctx_mem,
ctxsw_prog_main_image_priv_access_map_addr_lo_o(),
u64_lo32(addr));
nvgpu_mem_wr(g, ctx_mem,
ctxsw_prog_main_image_priv_access_map_addr_hi_o(),
u64_hi32(addr));
}
void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g,
struct nvgpu_mem *ctx_mem)
{

2
drivers/gpu/nvgpu/hal/init/hal_ga100.c
View File

@@ -446,8 +446,10 @@ static const struct gops_gr_ctxsw_prog ga100_ops_gr_ctxsw_prog = {
.set_patch_addr = gm20b_ctxsw_prog_set_patch_addr,
.init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data,
.set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta,
#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
.set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map,
.set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map,
#endif
.disable_verif_features = gm20b_ctxsw_prog_disable_verif_features,
.set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr,
.set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header,

2
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -410,8 +410,10 @@ static const struct gops_gr_ctxsw_prog ga10b_ops_gr_ctxsw_prog = {
.set_patch_addr = gm20b_ctxsw_prog_set_patch_addr,
.init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data,
.set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta,
#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
.set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map,
.set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map,
#endif
.disable_verif_features = gm20b_ctxsw_prog_disable_verif_features,
.set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr,
.set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header,

2
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -201,8 +201,10 @@ static const struct gops_gr_ctxsw_prog gm20b_ops_gr_ctxsw_prog = {
.set_patch_addr = gm20b_ctxsw_prog_set_patch_addr,
.init_ctxsw_hdr_data = gm20b_ctxsw_prog_init_ctxsw_hdr_data,
.set_compute_preemption_mode_cta = gm20b_ctxsw_prog_set_compute_preemption_mode_cta,
#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
.set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map,
.set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map,
#endif
.disable_verif_features = gm20b_ctxsw_prog_disable_verif_features,
#ifdef CONFIG_NVGPU_GRAPHICS
.set_zcull_ptr = gm20b_ctxsw_prog_set_zcull_ptr,

2
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -256,8 +256,10 @@ static const struct gops_gr_ctxsw_prog gp10b_ops_gr_ctxsw_prog = {
.set_patch_addr = gm20b_ctxsw_prog_set_patch_addr,
.init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data,
.set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta,
#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
.set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map,
.set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map,
#endif
.disable_verif_features = gm20b_ctxsw_prog_disable_verif_features,
#ifdef CONFIG_NVGPU_GRAPHICS
.set_zcull_ptr = gm20b_ctxsw_prog_set_zcull_ptr,

2
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -333,8 +333,10 @@ static const struct gops_gr_ctxsw_prog gv11b_ops_gr_ctxsw_prog = {
.set_patch_addr = gm20b_ctxsw_prog_set_patch_addr,
.init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data,
.set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta,
#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
.set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map,
.set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map,
#endif
.disable_verif_features = gm20b_ctxsw_prog_disable_verif_features,
.set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr,
.set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header,

2
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -377,8 +377,10 @@ static const struct gops_gr_ctxsw_prog tu104_ops_gr_ctxsw_prog = {
.set_patch_addr = gm20b_ctxsw_prog_set_patch_addr,
.init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data,
.set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta,
#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
.set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map,
.set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map,
#endif
.disable_verif_features = gm20b_ctxsw_prog_disable_verif_features,
.set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr,
.set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header,

2
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c
View File

@@ -280,8 +280,10 @@ static const struct gops_gr_ctxsw_prog vgpu_ga10b_ops_gr_ctxsw_prog = {
.set_patch_addr = gm20b_ctxsw_prog_set_patch_addr,
.init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data,
.set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta,
#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
.set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map,
.set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map,
#endif
.disable_verif_features = gm20b_ctxsw_prog_disable_verif_features,
#ifdef CONFIG_NVGPU_GRAPHICS
.set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr,

2
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
View File

@@ -251,8 +251,10 @@ static const struct gops_gr_ctxsw_prog vgpu_gv11b_ops_gr_ctxsw_prog = {
.set_patch_addr = gm20b_ctxsw_prog_set_patch_addr,
.init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data,
.set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta,
#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
.set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map,
.set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map,
#endif
.disable_verif_features = gm20b_ctxsw_prog_disable_verif_features,
#ifdef CONFIG_NVGPU_GRAPHICS
.set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr,

2
drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
View File

@@ -908,11 +908,13 @@ struct gops_gr_ctxsw_prog {
u64 addr);
void (*set_type_per_veid_header)(struct gk20a *g,
struct nvgpu_mem *ctx_mem);
#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
void (*set_priv_access_map_config_mode)(struct gk20a *g,
struct nvgpu_mem *ctx_mem, bool allow_all);
void (*set_priv_access_map_addr)(struct gk20a *g,
struct nvgpu_mem *ctx_mem,
u64 addr);
#endif
void (*disable_verif_features)(struct gk20a *g,
struct nvgpu_mem *ctx_mem);
void (*init_ctxsw_hdr_data)(struct gk20a *g,

2
userspace/units/gr/setup/nvgpu-gr-setup.h
View File

@@ -58,8 +58,6 @@ struct unit_module;
* nvgpu_gr_ctx_get_global_ctx_va,
* gops_gr_setup.alloc_obj_ctx,
* nvgpu_gr_ctx_load_golden_ctx_image,
* gm20b_ctxsw_prog_set_config_mode_priv_access_map,
* gm20b_ctxsw_prog_set_addr_priv_access_map,
* gm20b_ctxsw_prog_set_patch_addr,
* gm20b_ctxsw_prog_disable_verif_features,
* gv11b_gr_init_commit_global_attrib_cb,