gpu: nvgpu: RPPG support

- Added rppg module to init GR/MS-RPPG.
  mscg is dependent on gr-rppg & without
  gr-rppg engage mscg does not engage.
- Update pg engines HAL to return supported
  pg engines & its sub features

JIRA DNVGPU-71

Change-Id: Ib0fd2d79b509f6f2f1dabae6e2b5aebcc80b5691
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247486
(cherry picked from commit 86e45fa62e6a6b295f73c0173f0117ae9f78a5e9)
Reviewed-on: http://git-master/r/1270762
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/Makefile.nvgpu-t18x

@@ -62,7 +62,8 @@ nvgpu-y += \
 	$(nvgpu-t18x)/therm/thrm.o \
 	$(nvgpu-t18x)/therm/thrmdev.o \
 	$(nvgpu-t18x)/therm/thrmchannel.o \
-	$(nvgpu-t18x)/therm/thrmpmu.o
+	$(nvgpu-t18x)/therm/thrmpmu.o \
+	$(nvgpu-t18x)/lpwr/rppg.o
 
 nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o
 

drivers/gpu/nvgpu/gp106/pmu_gp106.c

@@ -24,6 +24,7 @@
 #include "clk/clk_mclk.h"
 #include "hw_mc_gp106.h"
 #include "hw_pwr_gp106.h"
+#include "lpwr/rppg.h"
 
 #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000
 #define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10
@@ -174,6 +175,67 @@ static bool gp106_is_pmu_supported(struct gk20a *g)
 	return true;
 }
 
+static u32 gp106_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id)
+{
+	if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS)
+		return PMU_PG_FEATURE_GR_RPPG_ENABLED;
+
+	return 0;
+}
+
+static u32 gp106_pmu_pg_engines_list(struct gk20a *g)
+{
+	return BIT(PMU_PG_ELPG_ENGINE_ID_GRAPHICS);
+}
+
+static void pmu_handle_param_msg(struct gk20a *g, struct pmu_msg *msg,
+			void *param, u32 handle, u32 status)
+{
+	gk20a_dbg_fn("");
+
+	if (status != 0) {
+		gk20a_err(dev_from_gk20a(g), "PG PARAM cmd aborted");
+		return;
+	}
+
+	gp106_dbg_pmu("PG PARAM is acknowledged from PMU %x",
+			msg->msg.pg.msg_type);
+}
+
+static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id)
+{
+	struct pmu_gk20a *pmu = &g->pmu;
+	struct pmu_cmd cmd;
+	u32 seq;
+	u32 status;
+
+	memset(&cmd, 0, sizeof(struct pmu_cmd));
+	if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) {
+
+		status = init_rppg(g);
+		if (status != 0) {
+			gk20a_err(dev_from_gk20a(g), "RPPG init Failed");
+			return -1;
+		}
+
+		cmd.hdr.unit_id = PMU_UNIT_PG;
+		cmd.hdr.size = PMU_CMD_HDR_SIZE +
+				sizeof(struct pmu_pg_cmd_gr_init_param);
+		cmd.cmd.pg.gr_init_param.cmd_type =
+				PMU_PG_CMD_ID_PG_PARAM;
+		cmd.cmd.pg.gr_init_param.sub_cmd_id =
+				PMU_PG_PARAM_CMD_GR_INIT_PARAM;
+		cmd.cmd.pg.gr_init_param.featuremask =
+				PMU_PG_FEATURE_GR_RPPG_ENABLED;
+
+		gp106_dbg_pmu("cmd post GR PMU_PG_CMD_ID_PG_PARAM");
+		gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+				pmu_handle_param_msg, pmu, &seq, ~0);
+	}
+
+	return 0;
+}
+
 void gp106_init_pmu_ops(struct gpu_ops *gops)
 {
 	gk20a_dbg_fn("");
@@ -195,10 +257,10 @@ void gp106_init_pmu_ops(struct gpu_ops *gops)
 	gops->pmu.lspmuwprinitdone = 0;
 	gops->pmu.fecsbootstrapdone = false;
 	gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase;
-	gops->pmu.pmu_elpg_statistics = NULL;
-	gops->pmu.pmu_pg_init_param = NULL;
-	gops->pmu.pmu_pg_supported_engines_list = NULL;
-	gops->pmu.pmu_pg_engines_feature_list = NULL;
+	gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics;
+	gops->pmu.pmu_pg_init_param = gp106_pg_param_init;
+	gops->pmu.pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list;
+	gops->pmu.pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list;
 	gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
 	gops->pmu.dump_secure_fuses = NULL;
 	gops->pmu.reset = gp106_falcon_reset;

drivers/gpu/nvgpu/gp106/pmu_gp106.h

@@ -14,6 +14,9 @@
 #ifndef __PMU_GP106_H_
 #define __PMU_GP106_H_
 
+#define gp106_dbg_pmu(fmt, arg...) \
+	gk20a_dbg(gpu_dbg_pmu, fmt, ##arg)
+
 void gp106_init_pmu_ops(struct gpu_ops *gops);
 
 #endif /*__PMU_GP106_H_*/

drivers/gpu/nvgpu/gp10b/pmu_gp10b.c

@@ -249,7 +249,8 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
 
 	return 0;
 }
-static void gp10b_pmu_elpg_statistics(struct gk20a *g,
+
+void gp10b_pmu_elpg_statistics(struct gk20a *g,
 		u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt)
 {
 	struct pmu_gk20a *pmu = &g->pmu;

drivers/gpu/nvgpu/gp10b/pmu_gp10b.h

@@ -20,5 +20,7 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops);
 int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask);
 int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id);
 void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr);
+void gp10b_pmu_elpg_statistics(struct gk20a *g,
+		u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt);
 
 #endif /*__PMU_GP10B_H_*/

drivers/gpu/nvgpu/lpwr/rppg.c

@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "gk20a/pmu_gk20a.h"
+#include "gp106/pmu_gp106.h"
+#include "gk20a/pmu_api.h"
+#include "gm206/bios_gm206.h"
+#include "pstate/pstate.h"
+#include "include/bios.h"
+#include "pmuif/gpmuif_pg_rppg.h"
+
+static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg,
+	void *param, u32 handle, u32 status)
+{
+
+	u8 ctrlId = NV_PMU_RPPG_CTRL_ID_MAX;
+	u32 *success = param;
+
+	if (status == 0) {
+		switch (msg->msg.pg.rppg_msg.cmn.msg_id) {
+		case NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK:
+			ctrlId = msg->msg.pg.rppg_msg.init_ctrl_ack.ctrl_id;
+			*success = 1;
+			gp106_dbg_pmu("RPPG is acknowledged from PMU %x",
+				msg->msg.pg.msg_type);
+		break;
+		}
+	}
+
+	gp106_dbg_pmu("RPPG is acknowledged from PMU %x",
+				msg->msg.pg.msg_type);
+}
+
+static u32 rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd)
+{
+	struct pmu_cmd cmd;
+	u32 seq;
+	u32 status = 0;
+	u32 success = 0;
+
+	memset(&cmd, 0, sizeof(struct pmu_cmd));
+	cmd.hdr.unit_id = PMU_UNIT_PG;
+	cmd.hdr.size   = PMU_CMD_HDR_SIZE +
+			sizeof(struct nv_pmu_rppg_cmd);
+
+	cmd.cmd.pg.rppg_cmd.cmn.cmd_type = PMU_PMU_PG_CMD_ID_RPPG;
+	cmd.cmd.pg.rppg_cmd.cmn.cmd_id   = prppg_cmd->cmn.cmd_id;
+
+	switch (prppg_cmd->cmn.cmd_id) {
+	case NV_PMU_RPPG_CMD_ID_INIT:
+		break;
+	case NV_PMU_RPPG_CMD_ID_INIT_CTRL:
+		cmd.cmd.pg.rppg_cmd.init_ctrl.ctrl_id =
+			prppg_cmd->init_ctrl.ctrl_id;
+		cmd.cmd.pg.rppg_cmd.init_ctrl.domain_id =
+			prppg_cmd->init_ctrl.domain_id;
+		break;
+	case NV_PMU_RPPG_CMD_ID_STATS_RESET:
+		cmd.cmd.pg.rppg_cmd.stats_reset.ctrl_id =
+			prppg_cmd->stats_reset.ctrl_id;
+		break;
+	default:
+		gk20a_err(dev_from_gk20a(g), "Inivalid RPPG command %d",
+			prppg_cmd->cmn.cmd_id);
+		return -1;
+	}
+
+	status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+			pmu_handle_rppg_init_msg, &success, &seq, ~0);
+	if (status) {
+		gk20a_err(dev_from_gk20a(g), "Unable to submit parameter command %d",
+			prppg_cmd->cmn.cmd_id);
+		goto exit;
+	}
+
+	if (prppg_cmd->cmn.cmd_id == NV_PMU_RPPG_CMD_ID_INIT_CTRL) {
+		pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g),
+			&success, 1);
+		if (success == 0) {
+			status = -EINVAL;
+			gk20a_err(dev_from_gk20a(g), "Ack for the parameter command %x",
+				prppg_cmd->cmn.cmd_id);
+		}
+	}
+
+exit:
+	return status;
+}
+
+static u32 rppg_init(struct gk20a *g)
+{
+	struct nv_pmu_rppg_cmd rppg_cmd;
+
+	rppg_cmd.init.cmd_id = NV_PMU_RPPG_CMD_ID_INIT;
+
+	return rppg_send_cmd(g, &rppg_cmd);
+}
+
+static u32 rppg_ctrl_init(struct gk20a *g, u8 ctrl_id)
+{
+	struct nv_pmu_rppg_cmd rppg_cmd;
+
+	rppg_cmd.init_ctrl.cmd_id  = NV_PMU_RPPG_CMD_ID_INIT_CTRL;
+	rppg_cmd.init_ctrl.ctrl_id = ctrl_id;
+
+	switch (ctrl_id) {
+	case NV_PMU_RPPG_CTRL_ID_GR:
+	case NV_PMU_RPPG_CTRL_ID_MS:
+		rppg_cmd.init_ctrl.domain_id = NV_PMU_RPPG_DOMAIN_ID_GFX;
+		break;
+	}
+
+	return rppg_send_cmd(g, &rppg_cmd);
+}
+
+u32 init_rppg(struct gk20a *g)
+{
+	u32 status;
+
+	status = rppg_init(g);
+	if (status != 0) {
+		gk20a_err(dev_from_gk20a(g),
+			"Failed to initialize RPPG in PMU: 0x%08x", status);
+		return status;
+	}
+
+
+	status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_GR);
+	if (status != 0) {
+		gk20a_err(dev_from_gk20a(g),
+			"Failed to initialize RPPG_CTRL: GR in PMU: 0x%08x",
+			status);
+		return status;
+	}
+
+	status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_MS);
+	if (status != 0) {
+		gk20a_err(dev_from_gk20a(g),
+			"Failed to initialize RPPG_CTRL: MS in PMU: 0x%08x",
+			status);
+		return status;
+	}
+
+	return status;
+}
+
+

drivers/gpu/nvgpu/lpwr/rppg.h

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#ifndef _RPPG_H_
+#define _RPPG_H_
+
+u32 init_rppg(struct gk20a *g);
+#endif