gpu: nvgpu: Add device_info_data support

Added device_info_data parsing
support for pascal GPU series.
This is required
to identify the (Logical CE)
NV_PTOP_DEVICE_INFO_TYPE_ENUM_LCE
instance id.
(example - CE0, CE1, CE2, CE3, ...)

JIRA DNVGPU-26

Change-Id: I35c42cb1d544729e4099db1528c690dd2be025f4
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1151605
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>

drivers/gpu/nvgpu/gp106/hw_top_gp106.h

@@ -158,6 +158,42 @@ static inline u32 top_device_info_entry_enum_v(void)
 {
 	return 0x00000002;
 }
+static inline u32 top_device_info_entry_data_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 top_device_info_data_type_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 top_device_info_data_type_enum2_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 top_device_info_data_inst_id_v(u32 r)
+{
+	return (r >> 26) & 0xf;
+}
+static inline u32 top_device_info_data_pri_base_v(u32 r)
+{
+	return (r >> 12) & 0xfff;
+}
+static inline u32 top_device_info_data_pri_base_align_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
+{
+	return (r >> 3) & 0x1f;
+}
+static inline u32 top_device_info_data_fault_id_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 top_device_info_data_fault_id_valid_v(void)
+{
+	return 0x00000001;
+}
 static inline u32 top_scratch1_r(void)
 {
 	return 0x0002240c;

drivers/gpu/nvgpu/gp10b/fifo_gp10b.c

@@ -182,7 +182,8 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
 	return 0;
 }
 
-static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type)
+static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
+					u32 *inst_id)
 {
 	int ret = ENGINE_INVAL_GK20A;
 
@@ -197,6 +198,28 @@ static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type)
 	return ret;
 }
 
+void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
+				u32 *inst_id, u32 *pri_base, u32 *fault_id)
+{
+	if (top_device_info_data_type_v(table_entry) ==
+	    top_device_info_data_type_enum2_v()) {
+		if (inst_id)
+			*inst_id = top_device_info_data_inst_id_v(table_entry);
+		if (pri_base) {
+			*pri_base =
+			    (top_device_info_data_pri_base_v(table_entry)
+			    << top_device_info_data_pri_base_align_v());
+		}
+		if (fault_id && (top_device_info_data_fault_id_v(table_entry) ==
+		    top_device_info_data_fault_id_valid_v())) {
+			*fault_id =
+			     top_device_info_data_fault_id_enum_v(table_entry);
+		}
+	} else
+		gk20a_err(g->dev, "unknown device_info_data %d",
+			top_device_info_data_type_v(table_entry));
+}
+
 void gp10b_init_fifo(struct gpu_ops *gops)
 {
 	gm20b_init_fifo(gops);
@@ -204,4 +227,5 @@ void gp10b_init_fifo(struct gpu_ops *gops)
 	gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature;
 	gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc;
 	gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type;
+	gops->fifo.device_info_data_parse = gp10b_device_info_data_parse;
 }

drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h

@@ -186,4 +186,40 @@ static inline u32 top_device_info_entry_engine_type_v(void)
 {
 	return 0x00000002;
 }
+static inline u32 top_device_info_entry_data_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 top_device_info_data_type_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 top_device_info_data_type_enum2_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 top_device_info_data_inst_id_v(u32 r)
+{
+	return (r >> 26) & 0xf;
+}
+static inline u32 top_device_info_data_pri_base_v(u32 r)
+{
+	return (r >> 12) & 0xfff;
+}
+static inline u32 top_device_info_data_pri_base_align_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
+{
+	return (r >> 3) & 0x1f;
+}
+static inline u32 top_device_info_data_fault_id_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 top_device_info_data_fault_id_valid_v(void)
+{
+	return 0x00000001;
+}
 #endif