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gpu: nvgpu: add flag for fecs trace support in rest of the units

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Add CONFIG_GK20A_CTXSW_TRACE flag for fecs trace support in rest of
the units like common.gr.utils and common.hal.gr.ctxsw_prog

Jira NVGPU-3414

Change-Id: I8f56bc38defd49a5fc30f79a35047afa7db2ffdf
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120277
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-05-16 17:04:41 +05:30
committed by mobile promotions
parent 4d3df9deae
commit 646b08a032
12 changed files with 24 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/gr/gr_utils.c
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@@ -74,11 +74,13 @@ struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g)
return g->gr->intr;
}
#ifdef CONFIG_GK20A_CTXSW_TRACE
struct nvgpu_gr_global_ctx_buffer_desc *nvgpu_gr_get_global_ctx_buffer_ptr(
struct gk20a *g)
{
return g->gr->global_ctx_buffer;
}
#endif
u32 nvgpu_gr_get_override_ecc_val(struct gk20a *g)
{

2
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -241,6 +241,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
.get_local_priv_register_ctl_offset =
gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
#ifdef CONFIG_GK20A_CTXSW_TRACE
.hw_get_ts_tag_invalid_timestamp =
gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,
.hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag,
@@ -253,6 +254,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
gm20b_ctxsw_prog_get_ts_buffer_aperture_mask,
.set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records,
.set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr,
#endif
.set_pmu_options_boost_clock_frequencies = NULL,
.set_full_preemption_ptr =
gp10b_ctxsw_prog_set_full_preemption_ptr,

2
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -276,6 +276,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
.get_local_priv_register_ctl_offset =
gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
#ifdef CONFIG_GK20A_CTXSW_TRACE
.hw_get_ts_tag_invalid_timestamp =
gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,
.hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag,
@@ -288,6 +289,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
gm20b_ctxsw_prog_get_ts_buffer_aperture_mask,
.set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records,
.set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr,
#endif
.set_pmu_options_boost_clock_frequencies = NULL,
.set_full_preemption_ptr =
gv11b_ctxsw_prog_set_full_preemption_ptr,

2
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c
View File

@@ -273,6 +273,7 @@ u32 gm20b_ctxsw_prog_get_local_priv_register_ctl_offset(u32 *context)
return ctxsw_prog_local_priv_register_ctl_offset_v(data);
}
#ifdef CONFIG_GK20A_CTXSW_TRACE
u32 gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp(void)
{
return ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v();
@@ -329,3 +330,4 @@ void gm20b_ctxsw_prog_set_ts_buffer_ptr(struct gk20a *g,
ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u64_hi32(addr)) |
aperture_mask);
}
#endif

2
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h
View File

@@ -76,6 +76,7 @@ void gm20b_ctxsw_prog_get_extended_buffer_size_offset(u32 *context,
u32 *size, u32 *offset);
void gm20b_ctxsw_prog_get_ppc_info(u32 *context, u32 *num_ppcs, u32 *ppc_mask);
u32 gm20b_ctxsw_prog_get_local_priv_register_ctl_offset(u32 *context);
#ifdef CONFIG_GK20A_CTXSW_TRACE
u32 gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp(void);
u32 gm20b_ctxsw_prog_hw_get_ts_tag(u64 ts);
u64 gm20b_ctxsw_prog_hw_record_ts_timestamp(u64 ts);
@@ -87,5 +88,6 @@ void gm20b_ctxsw_prog_set_ts_num_records(struct gk20a *g,
struct nvgpu_mem *ctx_mem, u32 num);
void gm20b_ctxsw_prog_set_ts_buffer_ptr(struct gk20a *g,
struct nvgpu_mem *ctx_mem, u64 addr, u32 aperture_mask);
#endif
#endif /* NVGPU_CTXSW_PROG_GM20B_H */

2
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -247,6 +247,7 @@ static const struct gpu_ops gm20b_ops = {
.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
.get_local_priv_register_ctl_offset =
gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
#ifdef CONFIG_GK20A_CTXSW_TRACE
.hw_get_ts_tag_invalid_timestamp =
gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,
.hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag,
@@ -259,6 +260,7 @@ static const struct gpu_ops gm20b_ops = {
gm20b_ctxsw_prog_get_ts_buffer_aperture_mask,
.set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records,
.set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr,
#endif
},
.config = {
.get_gpc_tpc_mask = gm20b_gr_config_get_gpc_tpc_mask,

2
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -286,6 +286,7 @@ static const struct gpu_ops gp10b_ops = {
.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
.get_local_priv_register_ctl_offset =
gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
#ifdef CONFIG_GK20A_CTXSW_TRACE
.hw_get_ts_tag_invalid_timestamp =
gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,
.hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag,
@@ -298,6 +299,7 @@ static const struct gpu_ops gp10b_ops = {
gm20b_ctxsw_prog_get_ts_buffer_aperture_mask,
.set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records,
.set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr,
#endif
.set_pmu_options_boost_clock_frequencies =
gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies,
.set_full_preemption_ptr =

2
drivers/gpu/nvgpu/hal/init/hal_gv100.c
View File

@@ -368,6 +368,7 @@ static const struct gpu_ops gv100_ops = {
.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
.get_local_priv_register_ctl_offset =
gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
#ifdef CONFIG_GK20A_CTXSW_TRACE
.hw_get_ts_tag_invalid_timestamp =
gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,
.hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag,
@@ -380,6 +381,7 @@ static const struct gpu_ops gv100_ops = {
gm20b_ctxsw_prog_get_ts_buffer_aperture_mask,
.set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records,
.set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr,
#endif
.set_pmu_options_boost_clock_frequencies =
gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies,
.set_full_preemption_ptr =

2
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -344,6 +344,7 @@ static const struct gpu_ops gv11b_ops = {
.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
.get_local_priv_register_ctl_offset =
gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
#ifdef CONFIG_GK20A_CTXSW_TRACE
.hw_get_ts_tag_invalid_timestamp =
gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,
.hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag,
@@ -356,6 +357,7 @@ static const struct gpu_ops gv11b_ops = {
gm20b_ctxsw_prog_get_ts_buffer_aperture_mask,
.set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records,
.set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr,
#endif
.set_pmu_options_boost_clock_frequencies =
gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies,
.set_full_preemption_ptr =

2
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -399,6 +399,7 @@ static const struct gpu_ops tu104_ops = {
.get_ppc_info = gm20b_ctxsw_prog_get_ppc_info,
.get_local_priv_register_ctl_offset =
gm20b_ctxsw_prog_get_local_priv_register_ctl_offset,
#ifdef CONFIG_GK20A_CTXSW_TRACE
.hw_get_ts_tag_invalid_timestamp =
gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp,
.hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag,
@@ -411,6 +412,7 @@ static const struct gpu_ops tu104_ops = {
gm20b_ctxsw_prog_get_ts_buffer_aperture_mask,
.set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records,
.set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr,
#endif
.set_pmu_options_boost_clock_frequencies =
gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies,
.set_full_preemption_ptr =

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -473,6 +473,7 @@ struct gpu_ops {
void (*get_ppc_info)(u32 *context,
u32 *num_ppcs, u32 *ppc_mask);
u32 (*get_local_priv_register_ctl_offset)(u32 *context);
#ifdef CONFIG_GK20A_CTXSW_TRACE
u32 (*hw_get_ts_tag_invalid_timestamp)(void);
u32 (*hw_get_ts_tag)(u64 ts);
u64 (*hw_record_ts_timestamp)(u64 ts);
@@ -485,6 +486,7 @@ struct gpu_ops {
void (*set_ts_buffer_ptr)(struct gk20a *g,
struct nvgpu_mem *ctx_mem, u64 addr,
u32 aperture_mask);
#endif
void (*set_pmu_options_boost_clock_frequencies)(
struct gk20a *g,
struct nvgpu_mem *ctx_mem, u32 boosted_ctx);

2
drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h
View File

@@ -42,8 +42,10 @@ struct nvgpu_gr_zbc *nvgpu_gr_get_zbc_ptr(struct gk20a *g);
struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g);
struct nvgpu_gr_hwpm_map *nvgpu_gr_get_hwpm_map_ptr(struct gk20a *g);
struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g);
#ifdef CONFIG_GK20A_CTXSW_TRACE
struct nvgpu_gr_global_ctx_buffer_desc *nvgpu_gr_get_global_ctx_buffer_ptr(
struct gk20a *g);
#endif
void nvgpu_gr_reset_falcon_ptr(struct gk20a *g);
void nvgpu_gr_reset_golden_image_ptr(struct gk20a *g);