gpu: nvgpu: gv100: MISRA 21.2 header guard fixes

MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gv100 hw headers
by renaming them to follow the convention, 'NVGPU_HEADER_NAME'.

JIRA NVGPU-1028

Change-Id: I78945233d16e47483b3c1f03fc0c7ca5774c3e95
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850997
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_bus_gv100_h_
-#define _hw_bus_gv100_h_
+#ifndef NVGPU_HW_BUS_GV100_H
+#define NVGPU_HW_BUS_GV100_H
 
 static inline u32 bus_sw_scratch_r(u32 i)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_ccsr_gv100_h_
-#define _hw_ccsr_gv100_h_
+#ifndef NVGPU_HW_CCSR_GV100_H
+#define NVGPU_HW_CCSR_GV100_H
 
 static inline u32 ccsr_channel_inst_r(u32 i)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_ce_gv100_h_
-#define _hw_ce_gv100_h_
+#ifndef NVGPU_HW_CE_GV100_H
+#define NVGPU_HW_CE_GV100_H
 
 static inline u32 ce_intr_status_r(u32 i)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_ctxsw_prog_gv100_h_
-#define _hw_ctxsw_prog_gv100_h_
+#ifndef NVGPU_HW_CTXSW_PROG_GV100_H
+#define NVGPU_HW_CTXSW_PROG_GV100_H
 
 static inline u32 ctxsw_prog_fecs_header_v(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_falcon_gv100_h_
-#define _hw_falcon_gv100_h_
+#ifndef NVGPU_HW_FALCON_GV100_H
+#define NVGPU_HW_FALCON_GV100_H
 
 static inline u32 falcon_falcon_irqsset_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_fb_gv100_h_
-#define _hw_fb_gv100_h_
+#ifndef NVGPU_HW_FB_GV100_H
+#define NVGPU_HW_FB_GV100_H
 
 static inline u32 fb_fbhub_num_active_ltcs_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_fifo_gv100_h_
-#define _hw_fifo_gv100_h_
+#ifndef NVGPU_HW_FIFO_GV100_H
+#define NVGPU_HW_FIFO_GV100_H
 
 static inline u32 fifo_userd_writeback_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_flush_gv100_h_
-#define _hw_flush_gv100_h_
+#ifndef NVGPU_HW_FLUSH_GV100_H
+#define NVGPU_HW_FLUSH_GV100_H
 
 static inline u32 flush_l2_system_invalidate_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_fuse_gv100_h_
-#define _hw_fuse_gv100_h_
+#ifndef NVGPU_HW_FUSE_GV100_H
+#define NVGPU_HW_FUSE_GV100_H
 
 static inline u32 fuse_status_opt_gpc_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_gmmu_gv100_h_
-#define _hw_gmmu_gv100_h_
+#ifndef NVGPU_HW_GMMU_GV100_H
+#define NVGPU_HW_GMMU_GV100_H
 
 static inline u32 gmmu_new_pde_is_pte_w(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_gr_gv100_h_
-#define _hw_gr_gv100_h_
+#ifndef NVGPU_HW_GR_GV100_H
+#define NVGPU_HW_GR_GV100_H
 
 static inline u32 gr_intr_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_ioctrl_gv100_h_
-#define _hw_ioctrl_gv100_h_
+#ifndef NVGPU_HW_IOCTRL_GV100_H
+#define NVGPU_HW_IOCTRL_GV100_H
 
 static inline u32 ioctrl_reset_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_ioctrlmif_gv100_h_
-#define _hw_ioctrlmif_gv100_h_
+#ifndef NVGPU_HW_IOCTRLMIF_GV100_H
+#define NVGPU_HW_IOCTRLMIF_GV100_H
 
 static inline u32 ioctrlmif_rx_err_contain_en_0_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_ltc_gv100_h_
-#define _hw_ltc_gv100_h_
+#ifndef NVGPU_HW_LTC_GV100_H
+#define NVGPU_HW_LTC_GV100_H
 
 static inline u32 ltc_pltcg_base_v(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_mc_gv100_h_
-#define _hw_mc_gv100_h_
+#ifndef NVGPU_HW_MC_GV100_H
+#define NVGPU_HW_MC_GV100_H
 
 static inline u32 mc_boot_0_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_minion_gv100_h_
-#define _hw_minion_gv100_h_
+#ifndef NVGPU_HW_MINION_GV100_H
+#define NVGPU_HW_MINION_GV100_H
 
 static inline u32 minion_minion_status_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_nvl_gv100_h_
-#define _hw_nvl_gv100_h_
+#ifndef NVGPU_HW_NVL_GV100_H
+#define NVGPU_HW_NVL_GV100_H
 
 static inline u32 nvl_link_state_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_nvlinkip_discovery_gv100_h_
-#define _hw_nvlinkip_discovery_gv100_h_
+#ifndef NVGPU_HW_NVLINKIP_DISCOVERY_GV100_H
+#define NVGPU_HW_NVLINKIP_DISCOVERY_GV100_H
 
 static inline u32 nvlinkip_discovery_common_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_nvlipt_gv100_h_
-#define _hw_nvlipt_gv100_h_
+#ifndef NVGPU_HW_NVLIPT_GV100_H
+#define NVGPU_HW_NVLIPT_GV100_H
 
 static inline u32 nvlipt_intr_control_link0_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_nvtlc_gv100_h_
-#define _hw_nvtlc_gv100_h_
+#ifndef NVGPU_HW_NVTLC_GV100_H
+#define NVGPU_HW_NVTLC_GV100_H
 
 static inline u32 nvtlc_tx_err_report_en_0_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_pbdma_gv100_h_
-#define _hw_pbdma_gv100_h_
+#ifndef NVGPU_HW_PBDMA_GV100_H
+#define NVGPU_HW_PBDMA_GV100_H
 
 static inline u32 pbdma_gp_entry1_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_pgsp_gv100_h_
-#define _hw_pgsp_gv100_h_
+#ifndef NVGPU_HW_PGSP_GV100_H
+#define NVGPU_HW_PGSP_GV100_H
 
 static inline u32 pgsp_falcon_irqsset_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_pram_gv100_h_
-#define _hw_pram_gv100_h_
+#ifndef NVGPU_HW_PRAM_GV100_H
+#define NVGPU_HW_PRAM_GV100_H
 
 static inline u32 pram_data032_r(u32 i)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_pri_ringmaster_gv100_h_
-#define _hw_pri_ringmaster_gv100_h_
+#ifndef NVGPU_HW_PRI_RINGMASTER_GV100_H
+#define NVGPU_HW_PRI_RINGMASTER_GV100_H
 
 static inline u32 pri_ringmaster_command_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_pri_ringstation_gpc_gv100_h_
-#define _hw_pri_ringstation_gpc_gv100_h_
+#ifndef NVGPU_HW_PRI_RINGSTATION_GPC_GV100_H
+#define NVGPU_HW_PRI_RINGSTATION_GPC_GV100_H
 
 static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_pri_ringstation_sys_gv100_h_
-#define _hw_pri_ringstation_sys_gv100_h_
+#ifndef NVGPU_HW_PRI_RINGSTATION_SYS_GV100_H
+#define NVGPU_HW_PRI_RINGSTATION_SYS_GV100_H
 
 static inline u32 pri_ringstation_sys_master_config_r(u32 i)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_proj_gv100_h_
-#define _hw_proj_gv100_h_
+#ifndef NVGPU_HW_PROJ_GV100_H
+#define NVGPU_HW_PROJ_GV100_H
 
 static inline u32 proj_gpc_base_v(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_pwr_gv100_h_
-#define _hw_pwr_gv100_h_
+#ifndef NVGPU_HW_PWR_GV100_H
+#define NVGPU_HW_PWR_GV100_H
 
 static inline u32 pwr_falcon_irqsset_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_ram_gv100_h_
-#define _hw_ram_gv100_h_
+#ifndef NVGPU_HW_RAM_GV100_H
+#define NVGPU_HW_RAM_GV100_H
 
 static inline u32 ram_in_ramfc_s(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_therm_gv100_h_
-#define _hw_therm_gv100_h_
+#ifndef NVGPU_HW_THERM_GV100_H
+#define NVGPU_HW_THERM_GV100_H
 
 static inline u32 therm_weight_1_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_timer_gv100_h_
-#define _hw_timer_gv100_h_
+#ifndef NVGPU_HW_TIMER_GV100_H
+#define NVGPU_HW_TIMER_GV100_H
 
 static inline u32 timer_pri_timeout_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_top_gv100_h_
-#define _hw_top_gv100_h_
+#ifndef NVGPU_HW_TOP_GV100_H
+#define NVGPU_HW_TOP_GV100_H
 
 static inline u32 top_num_gpcs_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_trim_gv100_h_
-#define _hw_trim_gv100_h_
+#ifndef NVGPU_HW_TRIM_GV100_H
+#define NVGPU_HW_TRIM_GV100_H
 
 static inline u32 trim_sys_nvlink_uphy_cfg_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_usermode_gv100_h_
-#define _hw_usermode_gv100_h_
+#ifndef NVGPU_HW_USERMODE_GV100_H
+#define NVGPU_HW_USERMODE_GV100_H
 
 static inline u32 usermode_cfg0_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_xp_gv100_h_
-#define _hw_xp_gv100_h_
+#ifndef NVGPU_HW_XP_GV100_H
+#define NVGPU_HW_XP_GV100_H
 
 static inline u32 xp_dl_mgr_r(u32 i)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_xve_gv100_h_
-#define _hw_xve_gv100_h_
+#ifndef NVGPU_HW_XVE_GV100_H
+#define NVGPU_HW_XVE_GV100_H
 
 static inline u32 xve_rom_ctrl_r(void)
 {

drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h

@@ -53,8 +53,8 @@
  *         comparison with unshifted values appropriate for use in field <y>
  *         of register <x>.
  */
-#ifndef _hw_perf_gv11b_h_
-#define _hw_perf_gv11b_h_
+#ifndef NVGPU_HW_PERF_GV11B_H
+#define NVGPU_HW_PERF_GV11B_H
 
 static inline u32 perf_pmmgpc_perdomain_offset_v(void)
 {