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gpu: nvgpu: update trace for sched params

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Use an inline function instead of a macro to
"expand" all channel parameters.

Jira EVLR-244
Jira EVLR-318

Change-Id: I4e8c5ee6bc9da36564af171be809f50dd2dfd439
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1150050
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Thomas Fleury
2016-03-15 19:06:43 -07:00
committed by Terje Bergstrom
parent 57a59616b5
commit 64f2e3ee9b
2 changed files with 29 additions and 24 deletions
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23
drivers/gpu/nvgpu/gk20a/channel_gk20a.c
View File

@@ -1196,7 +1196,8 @@ static int __gk20a_channel_open(struct gk20a *g, struct file *filp)
return -ENOMEM;
}
trace_gk20a_channel_sched_defaults(GK20A_TP_ARGS_SCHED(ch));
gk20a_channel_trace_sched_param(
trace_gk20a_channel_sched_defaults, ch);
filp->private_data = ch;
return 0;
@@ -3060,8 +3061,8 @@ long gk20a_channel_ioctl(struct file *filp,
gk20a_dbg(gpu_dbg_gpu_dbg, "setting timeout (%d ms) for chid %d",
timeout, ch->hw_chid);
ch->timeout_ms_max = timeout;
trace_gk20a_channel_set_timeout(GK20A_TP_ARGS_SCHED(ch));
gk20a_channel_trace_sched_param(
trace_gk20a_channel_set_timeout, ch);
break;
}
case NVGPU_IOCTL_CHANNEL_SET_TIMEOUT_EX:
@@ -3075,8 +3076,8 @@ long gk20a_channel_ioctl(struct file *filp,
timeout, ch->hw_chid);
ch->timeout_ms_max = timeout;
ch->timeout_debug_dump = timeout_debug_dump;
trace_gk20a_channel_set_timeout(GK20A_TP_ARGS_SCHED(ch));
gk20a_channel_trace_sched_param(
trace_gk20a_channel_set_timeout, ch);
break;
}
case NVGPU_IOCTL_CHANNEL_GET_TIMEDOUT:
@@ -3095,8 +3096,8 @@ long gk20a_channel_ioctl(struct file *filp,
((struct nvgpu_set_priority_args *)buf)->priority);
gk20a_idle(dev);
trace_gk20a_channel_set_priority(GK20A_TP_ARGS_SCHED(ch));
gk20a_channel_trace_sched_param(
trace_gk20a_channel_set_priority, ch);
break;
case NVGPU_IOCTL_CHANNEL_ENABLE:
err = gk20a_busy(dev);
@@ -3182,8 +3183,8 @@ long gk20a_channel_ioctl(struct file *filp,
((struct nvgpu_runlist_interleave_args *)buf)->level);
gk20a_idle(dev);
trace_gk20a_channel_set_runlist_interleave(GK20A_TP_ARGS_SCHED(ch));
gk20a_channel_trace_sched_param(
trace_gk20a_channel_set_runlist_interleave, ch);
break;
case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE:
err = gk20a_busy(dev);
@@ -3197,8 +3198,8 @@ long gk20a_channel_ioctl(struct file *filp,
((struct nvgpu_timeslice_args *)buf)->timeslice_us);
gk20a_idle(dev);
trace_gk20a_channel_set_timeslice(GK20A_TP_ARGS_SCHED(ch));
gk20a_channel_trace_sched_param(
trace_gk20a_channel_set_timeslice, ch);
break;
case NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE:
if (ch->g->ops.gr.set_preemption_mode) {

30
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -1064,18 +1064,22 @@ static inline struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch)
return tsg;
}
#define GK20A_TP_ARGS_SCHED(ch) \
ch->hw_chid, \
ch->tsgid, \
ch->pid, \
gk20a_is_channel_marked_as_tsg(ch) ? \
tsg_gk20a_from_ch(ch)->timeslice_us : ch->timeslice_us, \
ch->timeout_ms_max, \
gk20a_fifo_interleave_level_name(ch->interleave_level), \
gr_gk20a_graphics_preempt_mode_name(ch->ch_ctx.gr_ctx ? \
ch->ch_ctx.gr_ctx->graphics_preempt_mode : 0), \
gr_gk20a_compute_preempt_mode_name(ch->ch_ctx.gr_ctx ? \
ch->ch_ctx.gr_ctx->compute_preempt_mode : 0)
static inline void gk20a_channel_trace_sched_param(
void (*trace)(int chid, int tsgid, pid_t pid, u32 timeslice,
u32 timeout, const char *interleave,
const char *graphics_preempt_mode,
const char *compute_preempt_mode),
struct channel_gk20a *ch)
{
(trace)(ch->hw_chid, ch->tsgid, ch->pid,
gk20a_is_channel_marked_as_tsg(ch) ?
tsg_gk20a_from_ch(ch)->timeslice_us : ch->timeslice_us,
ch->timeout_ms_max,
gk20a_fifo_interleave_level_name(ch->interleave_level),
gr_gk20a_graphics_preempt_mode_name(ch->ch_ctx.gr_ctx ?
ch->ch_ctx.gr_ctx->graphics_preempt_mode : 0),
gr_gk20a_compute_preempt_mode_name(ch->ch_ctx.gr_ctx ?
ch->ch_ctx.gr_ctx->compute_preempt_mode : 0));
}
#endif /* GK20A_H */