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gpu:nvgpu:unit:Rename gp106 to gv100 fuse unit test

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Remove gp106 and add gv100 unit test
This is as a part of removing gp106 support
This adds testing for gv100 to the fuse unit test
Removes check_sec/non_sec as they are not used
Removes delta SRAM fuse as they are not present in GV100

Bug 200457373

Change-Id: I9bb4b714500eae01d0df00bb9f6842d4d4fbfd12
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1960034
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Abdul Salam
2018-11-29 12:16:04 +05:30
committed by mobile promotions
parent 2f03c5a703
commit 66729df1bb
7 changed files with 50 additions and 187 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/gpu/nvgpu/common/fuse/fuse_gp106.c
View File

@@ -30,14 +30,6 @@
#include <nvgpu/hw/gp106/hw_fuse_gp106.h>
int gp106_fuse_check_priv_security(struct gk20a *g)
{
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
return 0;
}
u32 gp106_fuse_read_vin_cal_fuse_rev(struct gk20a *g)
{
return fuse_vin_cal_fuse_rev_data_v(
@@ -91,10 +83,6 @@ int gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g,
data = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
break;
case CTRL_CLK_VIN_ID_SRAM:
data = gk20a_readl(g, fuse_vin_cal_sram_delta_r());
break;
default:
return -EINVAL;
}
@@ -127,14 +115,6 @@ int gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g,
fuse_vin_cal_gpc1_delta_icpt_frac_data_s();
break;
case CTRL_CLK_VIN_ID_SRAM:
interceptdata = (fuse_vin_cal_sram_delta_icpt_int_data_v(data) <<
fuse_vin_cal_sram_delta_icpt_frac_data_s()) +
fuse_vin_cal_sram_delta_icpt_frac_data_v(data);
interceptdata = (interceptdata * 1000U) >>
fuse_vin_cal_sram_delta_icpt_frac_data_s();
break;
default:
return -EINVAL;
}
@@ -163,7 +143,6 @@ int gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g,
case CTRL_CLK_VIN_ID_SYS:
case CTRL_CLK_VIN_ID_XBAR:
case CTRL_CLK_VIN_ID_LTC:
case CTRL_CLK_VIN_ID_SRAM:
slopedata =
(fuse_vin_cal_gpc1_delta_slope_int_data_v(data)) * 1000U;
break;
@@ -218,10 +197,6 @@ int gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g,
reg_val = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
break;
case CTRL_CLK_VIN_ID_SRAM:
reg_val = gk20a_readl(g, fuse_vin_cal_sram_delta_r());
break;
default:
return -EINVAL;
}

1
drivers/gpu/nvgpu/common/fuse/fuse_gp106.h
View File

@@ -27,7 +27,6 @@
struct gk20a;
int gp106_fuse_check_priv_security(struct gk20a *g);
u32 gp106_fuse_read_vin_cal_fuse_rev(struct gk20a *g);
int gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g,
u32 vin_id, u32 *slope,

2
userspace/units/fuse/Makefile
View File

@@ -23,7 +23,7 @@
OBJS = nvgpu-fuse.o \
nvgpu-fuse-gm20b.o \
nvgpu-fuse-gp10b.o \
nvgpu-fuse-gp106.o
nvgpu-fuse-gv100.o
MODULE = nvgpu-fuse
include ../Makefile.units

2
userspace/units/fuse/Makefile.tmk
View File

@@ -16,7 +16,7 @@ NVGPU_UNIT_NAME=nvgpu-fuse
NVGPU_UNIT_SRCS=nvgpu-fuse.c \
nvgpu-fuse-gp10b.c \
nvgpu-fuse-gm20b.c \
nvgpu-fuse-gp106.c
nvgpu-fuse-gv100.c
include $(NV_COMPONENT_DIR)/../Makefile.units.common.tmk

171
userspace/units/fuse/nvgpu-fuse-gp106.c → userspace/units/fuse/nvgpu-fuse-gv100.c
View File

@@ -30,108 +30,39 @@
#include "common/fuse/fuse_gm20b.h"
#include "nvgpu-fuse-priv.h"
#include "nvgpu-fuse-gp106.h"
#include "nvgpu-fuse-gv100.h"
/* register definitions for this block */
#define GP106_FUSE_REG_BASE 0x00021000U
#define GP106_FUSE_STATUS_OPT_PRIV_SEC_EN (GP106_FUSE_REG_BASE+0x434U)
#define GP106_FUSE_OPT_ADC_CAL_FUSE_REV (GP106_FUSE_REG_BASE+0x64CU)
#define GP106_FUSE_OPT_ADC_CAL_GPC0 (GP106_FUSE_REG_BASE+0x650U)
#define GP106_FUSE_OPT_ADC_CAL_GPC1_DELTA (GP106_FUSE_REG_BASE+0x654U)
#define GP106_FUSE_OPT_ADC_CAL_GPC2_DELTA (GP106_FUSE_REG_BASE+0x658U)
#define GP106_FUSE_OPT_ADC_CAL_GPC3_DELTA (GP106_FUSE_REG_BASE+0x65CU)
#define GP106_FUSE_OPT_ADC_CAL_GPC4_DELTA (GP106_FUSE_REG_BASE+0x660U)
#define GP106_FUSE_OPT_ADC_CAL_GPC5_DELTA (GP106_FUSE_REG_BASE+0x664U)
#define GP106_FUSE_OPT_ADC_CAL_SHARED_DELTA (GP106_FUSE_REG_BASE+0x668U)
#define GP106_FUSE_OPT_ADC_CAL_SRAM_DELTA (GP106_FUSE_REG_BASE+0x66CU)
#define GV100_FUSE_REG_BASE 0x00021000U
#define GV100_FUSE_STATUS_OPT_PRIV_SEC_EN (GV100_FUSE_REG_BASE+0x434U)
#define GV100_FUSE_OPT_ADC_CAL_FUSE_REV (GV100_FUSE_REG_BASE+0x64CU)
#define GV100_FUSE_OPT_ADC_CAL_GPC0 (GV100_FUSE_REG_BASE+0x650U)
#define GV100_FUSE_OPT_ADC_CAL_GPC1_DELTA (GV100_FUSE_REG_BASE+0x654U)
#define GV100_FUSE_OPT_ADC_CAL_GPC2_DELTA (GV100_FUSE_REG_BASE+0x658U)
#define GV100_FUSE_OPT_ADC_CAL_GPC3_DELTA (GV100_FUSE_REG_BASE+0x65CU)
#define GV100_FUSE_OPT_ADC_CAL_GPC4_DELTA (GV100_FUSE_REG_BASE+0x660U)
#define GV100_FUSE_OPT_ADC_CAL_GPC5_DELTA (GV100_FUSE_REG_BASE+0x664U)
#define GV100_FUSE_OPT_ADC_CAL_SHARED_DELTA (GV100_FUSE_REG_BASE+0x668U)
/* for common init args */
struct fuse_test_args gp106_init_args = {
.gpu_arch = 0x13,
.gpu_impl = 0x6,
.fuse_base_addr = GP106_FUSE_REG_BASE,
.sec_fuse_addr = GP106_FUSE_STATUS_OPT_PRIV_SEC_EN,
struct fuse_test_args gv100_init_args = {
.gpu_arch = 0x14,
.gpu_impl = 0x0,
.fuse_base_addr = GV100_FUSE_REG_BASE,
.sec_fuse_addr = GV100_FUSE_STATUS_OPT_PRIV_SEC_EN,
};
/*
* Verify fuse API check_priv_security() when security fuse is enabled.
* Tests with secure debug enabled and disabled.
*/
int test_fuse_gp106_check_sec(struct unit_module *m,
struct gk20a *g, void *__args)
{
int ret = UNIT_SUCCESS;
int result;
nvgpu_posix_io_writel_reg_space(g, GP106_FUSE_STATUS_OPT_PRIV_SEC_EN,
0x1);
result = g->ops.fuse.check_priv_security(g);
if (result != 0) {
unit_err(m, "%s: fuse_check_priv_security returned "
"error %d\n", __func__, result);
ret = UNIT_FAIL;
}
if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
unit_err(m, "%s: NVGPU_SEC_PRIVSECURITY disabled\n",
__func__);
ret = UNIT_FAIL;
}
if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) {
unit_err(m, "%s: NVGPU_SEC_SECUREGPCCS disabled\n",
__func__);
ret = UNIT_FAIL;
}
return ret;
}
/*
* Verify fuse API check_priv_security() when security fuse is enabled.
* GP106 always has security enabled.
*/
int test_fuse_gp106_check_non_sec(struct unit_module *m,
struct gk20a *g, void *__args)
{
int ret = UNIT_SUCCESS;
int result;
nvgpu_posix_io_writel_reg_space(g, GP106_FUSE_STATUS_OPT_PRIV_SEC_EN,
0x0);
result = g->ops.fuse.check_priv_security(g);
if (result != 0) {
unit_err(m, "%s: fuse_check_priv_security returned "
"error %d\n", __func__, result);
ret = UNIT_FAIL;
}
if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
unit_err(m, "%s: NVGPU_SEC_PRIVSECURITY enabled\n", __func__);
ret = UNIT_FAIL;
}
if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) {
unit_err(m, "%s: NVGPU_SEC_SECUREGPCCS enabled\n", __func__);
ret = UNIT_FAIL;
}
return ret;
}
/* Verify fuse API to read cal fuse revision */
int test_fuse_gp106_vin_cal_rev(struct unit_module *m,
int test_fuse_gv100_vin_cal_rev(struct unit_module *m,
struct gk20a *g, void *__args)
{
const u32 rev = 0x3;
u32 val;
int ret = UNIT_SUCCESS;
nvgpu_posix_io_writel_reg_space(g, GP106_FUSE_OPT_ADC_CAL_FUSE_REV,
nvgpu_posix_io_writel_reg_space(g, GV100_FUSE_OPT_ADC_CAL_FUSE_REV,
rev);
val = g->ops.fuse.read_vin_cal_fuse_rev(g);
@@ -203,30 +134,6 @@ static u32 gpc1_expected_intercept(u32 gpc0_fuse, u32 gpc1_fuse)
}
}
/* calculate slope value from GPC0 and delta SRAM fuse */
static u32 sram_expected_slope(u32 gpc0_fuse, u32 sram_fuse)
{
/*
* same calculation as GPC1, et al, but for consistency, make
* a new function
*/
return gpc1_expected_slope(gpc0_fuse, sram_fuse);
}
/* calculate intercept value from GPC0 and delta SRAM fuse */
static u32 sram_expected_intercept(u32 gpc0_fuse, u32 sram_fuse)
{
u32 gpc0_intercept = gpc0_expected_intercept(gpc0_fuse, gpc0_fuse);
u32 sram_delta = calculate_cal_unsigned(sram_fuse, 13, 9, 12, 1);
u32 sram_delta_positive = ((sram_fuse >> 22) & 0x1) == 0;
if (sram_delta_positive) {
return gpc0_intercept + sram_delta;
} else {
return gpc0_intercept - sram_delta;
}
}
static s8 fuse_expected_gain(u32 this_fuse)
{
return (s8)((this_fuse >> 16U) & 0x1fU);
@@ -242,7 +149,7 @@ static s8 fuse_expected_offset(u32 this_fuse)
* Loops through table of fuse values and expected results
* Validates invalid data checks
*/
int test_fuse_gp106_vin_cal_slope_intercept(struct unit_module *m,
int test_fuse_gv100_vin_cal_slope_intercept(struct unit_module *m,
struct gk20a *g, void *__args)
{
int result;
@@ -261,60 +168,50 @@ int test_fuse_gp106_vin_cal_slope_intercept(struct unit_module *m,
};
struct vin_test_struct vin_test_table[] = {
{
CTRL_CLK_VIN_ID_GPC0, GP106_FUSE_OPT_ADC_CAL_GPC0,
CTRL_CLK_VIN_ID_GPC0, GV100_FUSE_OPT_ADC_CAL_GPC0,
0x00214421, 0x00214421,
gpc0_expected_slope, gpc0_expected_intercept,
},
{
CTRL_CLK_VIN_ID_GPC1, GP106_FUSE_OPT_ADC_CAL_GPC1_DELTA,
CTRL_CLK_VIN_ID_GPC1, GV100_FUSE_OPT_ADC_CAL_GPC1_DELTA,
0x00214421, 0x00214421,
gpc1_expected_slope, gpc1_expected_intercept,
},
{
CTRL_CLK_VIN_ID_GPC2, GP106_FUSE_OPT_ADC_CAL_GPC2_DELTA,
CTRL_CLK_VIN_ID_GPC2, GV100_FUSE_OPT_ADC_CAL_GPC2_DELTA,
0x00000000, 0x00614c21,
gpc1_expected_slope, gpc1_expected_intercept,
},
{
CTRL_CLK_VIN_ID_GPC3, GP106_FUSE_OPT_ADC_CAL_GPC3_DELTA,
CTRL_CLK_VIN_ID_GPC3, GV100_FUSE_OPT_ADC_CAL_GPC3_DELTA,
0x00214421, 0xaaaaaaaa,
gpc1_expected_slope, gpc1_expected_intercept,
},
{
CTRL_CLK_VIN_ID_GPC4, GP106_FUSE_OPT_ADC_CAL_GPC4_DELTA,
CTRL_CLK_VIN_ID_GPC4, GV100_FUSE_OPT_ADC_CAL_GPC4_DELTA,
0x00214421, 0x55555555,
gpc1_expected_slope, gpc1_expected_intercept,
},
{
CTRL_CLK_VIN_ID_GPC5, GP106_FUSE_OPT_ADC_CAL_GPC5_DELTA,
CTRL_CLK_VIN_ID_GPC5, GV100_FUSE_OPT_ADC_CAL_GPC5_DELTA,
0x00214421, 0xefffffff,
gpc1_expected_slope, gpc1_expected_intercept,
},
{
CTRL_CLK_VIN_ID_SYS, GP106_FUSE_OPT_ADC_CAL_SHARED_DELTA,
CTRL_CLK_VIN_ID_SYS, GV100_FUSE_OPT_ADC_CAL_SHARED_DELTA,
0x00214421, 0xfffffffe,
gpc1_expected_slope, gpc1_expected_intercept,
},
{
CTRL_CLK_VIN_ID_XBAR, GP106_FUSE_OPT_ADC_CAL_SHARED_DELTA,
CTRL_CLK_VIN_ID_XBAR, GV100_FUSE_OPT_ADC_CAL_SHARED_DELTA,
0x00214421, 0x11111111,
gpc1_expected_slope, gpc1_expected_intercept,
},
{
CTRL_CLK_VIN_ID_LTC, GP106_FUSE_OPT_ADC_CAL_SHARED_DELTA,
CTRL_CLK_VIN_ID_LTC, GV100_FUSE_OPT_ADC_CAL_SHARED_DELTA,
0x00214421, 0x00000001,
gpc1_expected_slope, gpc1_expected_intercept,
},
{
CTRL_CLK_VIN_ID_SRAM, GP106_FUSE_OPT_ADC_CAL_SRAM_DELTA,
0x00214421, 0xaaaaaaaa,
sram_expected_slope, sram_expected_intercept,
},
{
CTRL_CLK_VIN_ID_SRAM, GP106_FUSE_OPT_ADC_CAL_SRAM_DELTA,
0x00214421, 0x55555555,
sram_expected_slope, sram_expected_intercept,
},
};
int vin_table_len = sizeof(vin_test_table)/sizeof(vin_test_table[0]);
int i;
@@ -325,7 +222,7 @@ int test_fuse_gp106_vin_cal_slope_intercept(struct unit_module *m,
u32 expected_slope, expected_intercept;
s8 expected_gain, expected_offset;
nvgpu_posix_io_writel_reg_space(g, GP106_FUSE_OPT_ADC_CAL_GPC0,
nvgpu_posix_io_writel_reg_space(g, GV100_FUSE_OPT_ADC_CAL_GPC0,
gpc0_fuse_val);
nvgpu_posix_io_writel_reg_space(g,
vin_test_table[i].fuse_addr,
@@ -388,7 +285,7 @@ int test_fuse_gp106_vin_cal_slope_intercept(struct unit_module *m,
}
/* test invalid GPC0 data special case */
nvgpu_posix_io_writel_reg_space(g, GP106_FUSE_OPT_ADC_CAL_GPC0,
nvgpu_posix_io_writel_reg_space(g, GV100_FUSE_OPT_ADC_CAL_GPC0,
~0U);
result = g->ops.fuse.read_vin_cal_slope_intercept_fuse(g,
CTRL_CLK_VIN_ID_GPC0,
@@ -407,11 +304,11 @@ int test_fuse_gp106_vin_cal_slope_intercept(struct unit_module *m,
ret = UNIT_FAIL;
}
/* restore valid data */
nvgpu_posix_io_writel_reg_space(g, GP106_FUSE_OPT_ADC_CAL_GPC0,
nvgpu_posix_io_writel_reg_space(g, GV100_FUSE_OPT_ADC_CAL_GPC0,
0U);
/* test invalid GPC1 data for the bad delta data case */
nvgpu_posix_io_writel_reg_space(g, GP106_FUSE_OPT_ADC_CAL_GPC1_DELTA,
nvgpu_posix_io_writel_reg_space(g, GV100_FUSE_OPT_ADC_CAL_GPC1_DELTA,
~0U);
result = g->ops.fuse.read_vin_cal_slope_intercept_fuse(g,
CTRL_CLK_VIN_ID_GPC1,
@@ -422,7 +319,7 @@ int test_fuse_gp106_vin_cal_slope_intercept(struct unit_module *m,
ret = UNIT_FAIL;
}
/* restore valid data */
nvgpu_posix_io_writel_reg_space(g, GP106_FUSE_OPT_ADC_CAL_GPC1_DELTA,
nvgpu_posix_io_writel_reg_space(g, GV100_FUSE_OPT_ADC_CAL_GPC1_DELTA,
0U);
/* test invalid VIN ID */
result = g->ops.fuse.read_vin_cal_slope_intercept_fuse(g,

16
userspace/units/fuse/nvgpu-fuse-gp106.h → userspace/units/fuse/nvgpu-fuse-gv100.h
View File

@@ -20,18 +20,14 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __UNIT_NVGPU_FUSE_GP106_H__
#define __UNIT_NVGPU_FUSE_GP106_H__
#ifndef __UNIT_NVGPU_FUSE_GV100_H__
#define __UNIT_NVGPU_FUSE_GV100_H__
extern struct fuse_test_args gp106_init_args;
extern struct fuse_test_args gv100_init_args;
int test_fuse_gp106_check_sec(struct unit_module *m,
struct gk20a *g, void *__args);
int test_fuse_gp106_check_non_sec(struct unit_module *m,
struct gk20a *g, void *__args);
int test_fuse_gp106_vin_cal_rev(struct unit_module *m,
int test_fuse_gv100_vin_cal_rev(struct unit_module *m,
struct gk20a *g, void *__args);
int test_fuse_gp106_vin_cal_slope_intercept(struct unit_module *m,
int test_fuse_gv100_vin_cal_slope_intercept(struct unit_module *m,
struct gk20a *g, void *__args);
#endif /* __UNIT_NVGPU_FUSE_GP106_H__ */
#endif /* __UNIT_NVGPU_FUSE_GV100_H__ */

20
userspace/units/fuse/nvgpu-fuse.c
View File

@@ -31,7 +31,7 @@
#include "nvgpu-fuse-priv.h"
#include "nvgpu-fuse-gp10b.h"
#include "nvgpu-fuse-gm20b.h"
#include "nvgpu-fuse-gp106.h"
#include "nvgpu-fuse-gv100.h"
/*
* Mock I/O
@@ -174,18 +174,14 @@ struct unit_module_test fuse_tests[] = {
UNIT_TEST(fuse_gm20b_cleanup, test_fuse_device_common_cleanup,
&gm20b_init_args),
UNIT_TEST(fuse_gp106_init, test_fuse_device_common_init,
&gp106_init_args),
UNIT_TEST(fuse_gp106_check_sec, test_fuse_gp106_check_sec, NULL),
UNIT_TEST(fuse_gp106_check_non_sec,
test_fuse_gp106_check_non_sec,
UNIT_TEST(fuse_gv100_init, test_fuse_device_common_init,
&gv100_init_args),
UNIT_TEST(fuse_gv100_vin_cal_rev, test_fuse_gv100_vin_cal_rev, NULL),
UNIT_TEST(fuse_gv100_vin_cal_slope_intercept,
test_fuse_gv100_vin_cal_slope_intercept,
NULL),
UNIT_TEST(fuse_gp106_vin_cal_rev, test_fuse_gp106_vin_cal_rev, NULL),
UNIT_TEST(fuse_gp106_vin_cal_slope_intercept,
test_fuse_gp106_vin_cal_slope_intercept,
NULL),
UNIT_TEST(fuse_gp106_cleanup, test_fuse_device_common_cleanup,
&gp106_init_args),
UNIT_TEST(fuse_gv100_cleanup, test_fuse_device_common_cleanup,
&gv100_init_args),
};
UNIT_MODULE(fuse, fuse_tests, UNIT_PRIO_NVGPU_TEST);