nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: moved & renamed "struct pmu_gk20a"

Browse Source 
- Renamed "struct pmu_gk20a" to "struct nvgpu_pmu" then moved
to file "pmu.h" under folder "drivers/gpu/nvgpu/include/nvgpu/"

- Included header file "pmu.h" to dependent file &
removed "pmu_gk20a.h" include if its usage is not present.

- Replaced "struct pmu_gk20a" with "struct nvgpu_pmu" in dependent
source & header files.

JIRA NVGPU-56

Change-Id: Ia3c606616831027093d5c216959c6a40d7c2632e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1479209
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2017-05-10 20:35:24 +05:30
committed by mobile promotions
parent 7668ccb2a2
commit 673dd97160
42 changed files with 615 additions and 589 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/boardobj/boardobj.h
View File

@@ -14,12 +14,12 @@
#ifndef _BOARDOBJ_H_
#define _BOARDOBJ_H_
struct boardobj;
#include "gk20a/pmu_gk20a.h"
#include "ctrl/ctrlboardobj.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "ctrl/ctrlboardobj.h"
struct boardobj;
/*
* check whether the specified BOARDOBJ object implements the queried
* type/class enumeration.

6
drivers/gpu/nvgpu/boardobj/boardobjgrp.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -10,15 +10,13 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <nvgpu/bug.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
#include "boardobjgrp.h"
#include "ctrl/ctrlboardobj.h"
#include "boardobj.h"
#include <nvgpu/bug.h>
static boardobjgrp_objinsert boardobjgrp_objinsert_final;
static boardobjgrp_objgetbyidx boardobjgrp_objgetbyidx_final;
static boardobjgrp_objgetnext boardobjgrp_objgetnext_final;

1
drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.h
View File

@@ -14,7 +14,6 @@
#ifndef _BOARDOBJGRP_E255_H_
#define _BOARDOBJGRP_E255_H_
#include "gk20a/pmu_gk20a.h"
#include "ctrl/ctrlboardobj.h"
#include "boardobj.h"
#include "boardobjgrpmask.h"

1
drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.h
View File

@@ -14,7 +14,6 @@
#ifndef _BOARDOBJGRP_E32_H_
#define _BOARDOBJGRP_E32_H_
#include "gk20a/pmu_gk20a.h"
#include "ctrl/ctrlboardobj.h"
#include "boardobj.h"
#include "boardobjgrp.h"

5
drivers/gpu/nvgpu/clk/clk.c
View File

@@ -11,13 +11,14 @@
* more details.
*/
#include <nvgpu/pmu.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "gk20a/gk20a.h"
#include "clk.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "volt/volt.h"
#include "gk20a/pmu_gk20a.h"
#define BOOT_GPC2CLK_MHZ 2581
#define BOOT_MCLK_MHZ 3003

1
drivers/gpu/nvgpu/clk/clk_domain.c
View File

@@ -21,7 +21,6 @@
#include "boardobj/boardobjgrp_e32.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
static struct clk_domain *construct_clk_domain(struct gk20a *g, void *pargs);

1
drivers/gpu/nvgpu/clk/clk_fll.c
View File

@@ -20,7 +20,6 @@
#include "boardobj/boardobjgrp_e32.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
static u32 devinit_get_fll_device_table(struct gk20a *g,
struct avfsfllobjs *pfllobjs);

1
drivers/gpu/nvgpu/clk/clk_freq_controller.c
View File

@@ -22,7 +22,6 @@
#include "boardobj/boardobjgrp_e32.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
static u32 clk_freq_controller_pmudatainit_super(struct gk20a *g,
struct boardobj *board_obj_ptr,

1
drivers/gpu/nvgpu/clk/clk_mclk.c
View File

@@ -17,7 +17,6 @@
#include <nvgpu/kmem.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
#ifdef CONFIG_DEBUG_FS
#include "gk20a/platform_gk20a.h"
#endif

2
drivers/gpu/nvgpu/clk/clk_prog.c
View File

@@ -12,7 +12,6 @@
*/
#include <nvgpu/bios.h>
#include <nvgpu/kmem.h>
#include "gk20a/gk20a.h"
@@ -24,7 +23,6 @@
#include "gm206/bios_gm206.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
static struct clk_prog *construct_clk_prog(struct gk20a *g, void *pargs);
static u32 devinit_get_clk_prog_table(struct gk20a *g,

2
drivers/gpu/nvgpu/clk/clk_vf_point.c
View File

@@ -11,6 +11,7 @@
* more details.
*/
#include "gk20a/gk20a.h"
#include "clk.h"
#include "clk_vf_point.h"
@@ -18,7 +19,6 @@
#include "boardobj/boardobjgrp_e32.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
static u32 _clk_vf_point_pmudatainit_super(struct gk20a *g, struct boardobj
*board_obj_ptr, struct nv_pmu_boardobj *ppmudata);

4
drivers/gpu/nvgpu/clk/clk_vin.c
View File

@@ -12,18 +12,16 @@
*/
#include <nvgpu/bios.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "gk20a/gk20a.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "ctrl/ctrlvolt.h"
#include "gm206/bios_gm206.h"
#include "gk20a/pmu_gk20a.h"
#include "clk.h"
#include "clk_vin.h"

2
drivers/gpu/nvgpu/common/linux/debug_pmu.c
View File

@@ -252,7 +252,7 @@ static const struct file_operations elpg_transitions_fops = {
static int falc_trace_show(struct seq_file *s, void *data)
{
struct gk20a *g = s->private;
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
u32 i = 0, j = 0, k, l, m;
char part_str[40];
void *tracebuffer;

53
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -50,6 +50,7 @@ struct gk20a_debug_output;
#include <nvgpu/acr/nvgpu_acr.h>
#include <nvgpu/kref.h>
#include <nvgpu/falcon.h>
#include <nvgpu/pmu.h>
#include "clk_gk20a.h"
#include "ce2_gk20a.h"
@@ -523,33 +524,33 @@ struct gpu_ops {
/*used for change of enum zbc update cmd id from ver 0 to ver1*/
u32 cmd_id_zbc_table_update;
bool is_pmu_zbc_save_supported;
u32 (*get_pmu_cmdline_args_size)(struct pmu_gk20a *pmu);
void (*set_pmu_cmdline_args_cpu_freq)(struct pmu_gk20a *pmu,
u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu);
void (*set_pmu_cmdline_args_cpu_freq)(struct nvgpu_pmu *pmu,
u32 freq);
void (*set_pmu_cmdline_args_trace_size)(struct pmu_gk20a *pmu,
void (*set_pmu_cmdline_args_trace_size)(struct nvgpu_pmu *pmu,
u32 size);
void (*set_pmu_cmdline_args_trace_dma_base)(
struct pmu_gk20a *pmu);
struct nvgpu_pmu *pmu);
void (*set_pmu_cmdline_args_trace_dma_idx)(
struct pmu_gk20a *pmu, u32 idx);
void * (*get_pmu_cmdline_args_ptr)(struct pmu_gk20a *pmu);
u32 (*get_pmu_allocation_struct_size)(struct pmu_gk20a *pmu);
void (*set_pmu_allocation_ptr)(struct pmu_gk20a *pmu,
struct nvgpu_pmu *pmu, u32 idx);
void * (*get_pmu_cmdline_args_ptr)(struct nvgpu_pmu *pmu);
u32 (*get_pmu_allocation_struct_size)(struct nvgpu_pmu *pmu);
void (*set_pmu_allocation_ptr)(struct nvgpu_pmu *pmu,
void **pmu_alloc_ptr, void *assign_ptr);
void (*pmu_allocation_set_dmem_size)(struct pmu_gk20a *pmu,
void (*pmu_allocation_set_dmem_size)(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr, u16 size);
u16 (*pmu_allocation_get_dmem_size)(struct pmu_gk20a *pmu,
u16 (*pmu_allocation_get_dmem_size)(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr);
u32 (*pmu_allocation_get_dmem_offset)(struct pmu_gk20a *pmu,
u32 (*pmu_allocation_get_dmem_offset)(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr);
u32 * (*pmu_allocation_get_dmem_offset_addr)(
struct pmu_gk20a *pmu, void *pmu_alloc_ptr);
void (*pmu_allocation_set_dmem_offset)(struct pmu_gk20a *pmu,
struct nvgpu_pmu *pmu, void *pmu_alloc_ptr);
void (*pmu_allocation_set_dmem_offset)(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr, u32 offset);
void * (*pmu_allocation_get_fb_addr)(
struct pmu_gk20a *pmu, void *pmu_alloc_ptr);
struct nvgpu_pmu *pmu, void *pmu_alloc_ptr);
u32 (*pmu_allocation_get_fb_size)(
struct pmu_gk20a *pmu, void *pmu_alloc_ptr);
struct nvgpu_pmu *pmu, void *pmu_alloc_ptr);
void (*get_pmu_init_msg_pmu_queue_params)(
struct pmu_queue *queue, u32 id,
void *pmu_init_msg);
@@ -590,15 +591,15 @@ struct gpu_ops {
struct pmu_sequence *seq);
void *(*get_pmu_seq_out_a_ptr)(
struct pmu_sequence *seq);
void (*set_pmu_cmdline_args_secure_mode)(struct pmu_gk20a *pmu,
void (*set_pmu_cmdline_args_secure_mode)(struct nvgpu_pmu *pmu,
u32 val);
u32 (*get_perfmon_cntr_sz)(struct pmu_gk20a *pmu);
void * (*get_perfmon_cntr_ptr)(struct pmu_gk20a *pmu);
void (*set_perfmon_cntr_ut)(struct pmu_gk20a *pmu, u16 ut);
void (*set_perfmon_cntr_lt)(struct pmu_gk20a *pmu, u16 lt);
void (*set_perfmon_cntr_valid)(struct pmu_gk20a *pmu, u8 val);
void (*set_perfmon_cntr_index)(struct pmu_gk20a *pmu, u8 val);
void (*set_perfmon_cntr_group_id)(struct pmu_gk20a *pmu,
u32 (*get_perfmon_cntr_sz)(struct nvgpu_pmu *pmu);
void * (*get_perfmon_cntr_ptr)(struct nvgpu_pmu *pmu);
void (*set_perfmon_cntr_ut)(struct nvgpu_pmu *pmu, u16 ut);
void (*set_perfmon_cntr_lt)(struct nvgpu_pmu *pmu, u16 lt);
void (*set_perfmon_cntr_valid)(struct nvgpu_pmu *pmu, u8 val);
void (*set_perfmon_cntr_index)(struct nvgpu_pmu *pmu, u8 val);
void (*set_perfmon_cntr_group_id)(struct nvgpu_pmu *pmu,
u8 gid);
u8 (*pg_cmd_eng_buf_load_size)(struct pmu_pg_cmd *pg);
@@ -728,7 +729,7 @@ struct gpu_ops {
bool (*is_pmu_supported)(struct gk20a *g);
int (*prepare_ucode)(struct gk20a *g);
int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g);
int (*pmu_nsbootstrap)(struct pmu_gk20a *pmu);
int (*pmu_nsbootstrap)(struct nvgpu_pmu *pmu);
int (*pmu_setup_elpg)(struct gk20a *g);
u32 (*pmu_get_queue_head)(u32 i);
u32 (*pmu_get_queue_head_size)(void);
@@ -1014,7 +1015,7 @@ struct gk20a {
struct gr_gk20a gr;
struct sim_gk20a sim;
struct mm_gk20a mm;
struct pmu_gk20a pmu;
struct nvgpu_pmu pmu;
struct acr_desc acr;
struct ecc_gk20a ecc;
struct cooling_device_gk20a gk20a_cdev;
@@ -1396,7 +1397,7 @@ static inline struct gk20a *gk20a_from_as(struct gk20a_as *as)
{
return container_of(as, struct gk20a, as);
}
static inline struct gk20a *gk20a_from_pmu(struct pmu_gk20a *pmu)
static inline struct gk20a *gk20a_from_pmu(struct nvgpu_pmu *pmu)
{
return container_of(pmu, struct gk20a, pmu);
}

4
drivers/gpu/nvgpu/gk20a/gk20a_scale.c
View File

@@ -24,15 +24,13 @@
#include <governor.h>
#include <nvgpu/kmem.h>
#include <nvgpu/log.h>
#include "gk20a.h"
#include "platform_gk20a.h"
#include "pmu_gk20a.h"
#include "clk_gk20a.h"
#include "gk20a_scale.h"
#include <nvgpu/log.h>
/*
* gk20a_scale_qos_notify()
*

2
drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
View File

@@ -491,7 +491,7 @@ static ssize_t mscg_enable_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct gk20a *g = get_gk20a(dev);
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
unsigned long val = 0;
int err;

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -5193,7 +5193,7 @@ clean_up:
static int gk20a_init_gr_bind_fecs_elpg(struct gk20a *g)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct mm_gk20a *mm = &g->mm;
struct vm_gk20a *vm = &mm->pmu.vm;
int err = 0;

318
drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
View File

File diff suppressed because it is too large Load Diff

324
drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
View File

@@ -24,14 +24,10 @@
#include <linux/version.h>
#include <nvgpu/flcnif_cmn.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include <nvgpu/pmu.h>
struct nvgpu_firmware;
/* defined by pmu hw spec */
#define GK20A_PMU_VA_SIZE (512 * 1024 * 1024)
#define GK20A_PMU_UCODE_SIZE_MAX (256 * 1024)
#define GK20A_PMU_SEQ_BUF_SIZE 4096
#define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe)
#define APP_VERSION_NC_3 21688026
@@ -56,127 +52,11 @@ struct nvgpu_firmware;
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
#define FUSE_GCPLEX_CONFIG_FUSE_0 0x2C8
#endif
#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6
#define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEAD
enum {
GK20A_PMU_DMAIDX_UCODE = 0,
GK20A_PMU_DMAIDX_VIRT = 1,
GK20A_PMU_DMAIDX_PHYS_VID = 2,
GK20A_PMU_DMAIDX_PHYS_SYS_COH = 3,
GK20A_PMU_DMAIDX_PHYS_SYS_NCOH = 4,
GK20A_PMU_DMAIDX_RSVD = 5,
GK20A_PMU_DMAIDX_PELPG = 6,
GK20A_PMU_DMAIDX_END = 7
};
#define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */
#define GK20A_PMU_DMEM_BLKSIZE2 8
#define GK20A_PMU_UCODE_NB_MAX_OVERLAY 32
#define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH 64
struct pmu_ucode_desc {
u32 descriptor_size;
u32 image_size;
u32 tools_version;
u32 app_version;
char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH];
u32 bootloader_start_offset;
u32 bootloader_size;
u32 bootloader_imem_offset;
u32 bootloader_entry_point;
u32 app_start_offset;
u32 app_size;
u32 app_imem_offset;
u32 app_imem_entry;
u32 app_dmem_offset;
u32 app_resident_code_offset; /* Offset from appStartOffset */
u32 app_resident_code_size; /* Exact size of the resident code ( potentially contains CRC inside at the end ) */
u32 app_resident_data_offset; /* Offset from appStartOffset */
u32 app_resident_data_size; /* Exact size of the resident code ( potentially contains CRC inside at the end ) */
u32 nb_overlays;
struct {u32 start; u32 size;} load_ovl[GK20A_PMU_UCODE_NB_MAX_OVERLAY];
u32 compressed;
};
struct pmu_ucode_desc_v1 {
u32 descriptor_size;
u32 image_size;
u32 tools_version;
u32 app_version;
char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH];
u32 bootloader_start_offset;
u32 bootloader_size;
u32 bootloader_imem_offset;
u32 bootloader_entry_point;
u32 app_start_offset;
u32 app_size;
u32 app_imem_offset;
u32 app_imem_entry;
u32 app_dmem_offset;
u32 app_resident_code_offset;
u32 app_resident_code_size;
u32 app_resident_data_offset;
u32 app_resident_data_size;
u32 nb_imem_overlays;
u32 nb_dmem_overlays;
struct {u32 start; u32 size; } load_ovl[64];
u32 compressed;
};
#define PMU_PGENG_GR_BUFFER_IDX_INIT (0)
#define PMU_PGENG_GR_BUFFER_IDX_ZBC (1)
#define PMU_PGENG_GR_BUFFER_IDX_FECS (2)
struct pmu_gk20a;
struct pmu_queue;
struct pmu_queue {
/* used by hw, for BIOS/SMI queue */
u32 mutex_id;
u32 mutex_lock;
/* used by sw, for LPQ/HPQ queue */
struct nvgpu_mutex mutex;
/* current write position */
u32 position;
/* physical dmem offset where this queue begins */
u32 offset;
/* logical queue identifier */
u32 id;
/* physical queue index */
u32 index;
/* in bytes */
u32 size;
/* open-flag */
u32 oflag;
bool opened; /* opened implies locked */
};
struct pmu_mutex {
u32 id;
u32 index;
u32 ref_cnt;
};
#define PMU_MAX_NUM_SEQUENCES (256)
#define PMU_SEQ_BIT_SHIFT (5)
#define PMU_SEQ_TBL_SIZE \
(PMU_MAX_NUM_SEQUENCES >> PMU_SEQ_BIT_SHIFT)
#define PMU_INVALID_SEQ_DESC (~0)
enum
{
PMU_SEQ_STATE_FREE = 0,
PMU_SEQ_STATE_PENDING,
PMU_SEQ_STATE_USED,
PMU_SEQ_STATE_CANCELLED
};
struct pmu_payload {
struct {
void *buf;
@@ -192,33 +72,6 @@ struct pmu_surface {
struct flcn_mem_desc_v0 params;
};
typedef void (*pmu_callback)(struct gk20a *, struct pmu_msg *, void *, u32,
u32);
struct pmu_sequence {
u8 id;
u32 state;
u32 desc;
struct pmu_msg *msg;
union {
struct pmu_allocation_v0 in_v0;
struct pmu_allocation_v1 in_v1;
struct pmu_allocation_v2 in_v2;
struct pmu_allocation_v3 in_v3;
};
struct nvgpu_mem *in_mem;
union {
struct pmu_allocation_v0 out_v0;
struct pmu_allocation_v1 out_v1;
struct pmu_allocation_v2 out_v2;
struct pmu_allocation_v3 out_v3;
};
struct nvgpu_mem *out_mem;
u8 *out_payload;
pmu_callback callback;
void* cb_params;
};
/*PG defines used by nvpgu-pmu*/
struct pmu_pg_stats_data {
u32 gating_cnt;
@@ -263,147 +116,6 @@ struct pmu_pg_stats_data {
#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200)
/*PG defines used by nvpgu-pmu*/
/* Falcon Register index */
#define PMU_FALCON_REG_R0 (0)
#define PMU_FALCON_REG_R1 (1)
#define PMU_FALCON_REG_R2 (2)
#define PMU_FALCON_REG_R3 (3)
#define PMU_FALCON_REG_R4 (4)
#define PMU_FALCON_REG_R5 (5)
#define PMU_FALCON_REG_R6 (6)
#define PMU_FALCON_REG_R7 (7)
#define PMU_FALCON_REG_R8 (8)
#define PMU_FALCON_REG_R9 (9)
#define PMU_FALCON_REG_R10 (10)
#define PMU_FALCON_REG_R11 (11)
#define PMU_FALCON_REG_R12 (12)
#define PMU_FALCON_REG_R13 (13)
#define PMU_FALCON_REG_R14 (14)
#define PMU_FALCON_REG_R15 (15)
#define PMU_FALCON_REG_IV0 (16)
#define PMU_FALCON_REG_IV1 (17)
#define PMU_FALCON_REG_UNDEFINED (18)
#define PMU_FALCON_REG_EV (19)
#define PMU_FALCON_REG_SP (20)
#define PMU_FALCON_REG_PC (21)
#define PMU_FALCON_REG_IMB (22)
#define PMU_FALCON_REG_DMB (23)
#define PMU_FALCON_REG_CSW (24)
#define PMU_FALCON_REG_CCR (25)
#define PMU_FALCON_REG_SEC (26)
#define PMU_FALCON_REG_CTX (27)
#define PMU_FALCON_REG_EXCI (28)
#define PMU_FALCON_REG_RSVD0 (29)
#define PMU_FALCON_REG_RSVD1 (30)
#define PMU_FALCON_REG_RSVD2 (31)
#define PMU_FALCON_REG_SIZE (32)
/* Choices for pmu_state */
#define PMU_STATE_OFF 0 /* PMU is off */
#define PMU_STATE_STARTING 1 /* PMU is on, but not booted */
#define PMU_STATE_INIT_RECEIVED 2 /* PMU init message received */
#define PMU_STATE_ELPG_BOOTING 3 /* PMU is booting */
#define PMU_STATE_ELPG_BOOTED 4 /* ELPG is initialized */
#define PMU_STATE_LOADING_PG_BUF 5 /* Loading PG buf */
#define PMU_STATE_LOADING_ZBC 6 /* Loading ZBC buf */
#define PMU_STATE_STARTED 7 /* Fully unitialized */
#define PMU_STATE_EXIT 8 /* Exit PMU state machine */
struct nvgpu_pg_init {
bool state_change;
struct nvgpu_cond wq;
struct nvgpu_thread state_task;
};
struct pmu_gk20a {
union {
struct pmu_ucode_desc *desc;
struct pmu_ucode_desc_v1 *desc_v1;
};
struct nvgpu_mem ucode;
struct nvgpu_mem pg_buf;
/* TBD: remove this if ZBC seq is fixed */
struct nvgpu_mem seq_buf;
struct nvgpu_mem trace_buf;
struct nvgpu_mem wpr_buf;
bool buf_loaded;
struct pmu_sha1_gid gid_info;
struct pmu_queue queue[PMU_QUEUE_COUNT];
struct pmu_sequence *seq;
unsigned long pmu_seq_tbl[PMU_SEQ_TBL_SIZE];
u32 next_seq_desc;
struct pmu_mutex *mutex;
u32 mutex_cnt;
struct nvgpu_mutex pmu_copy_lock;
struct nvgpu_mutex pmu_seq_lock;
struct nvgpu_allocator dmem;
u32 *ucode_image;
bool pmu_ready;
u32 zbc_save_done;
u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE];
u32 elpg_stat;
u32 mscg_stat;
u32 mscg_transition_state;
int pmu_state;
#define PMU_ELPG_ENABLE_ALLOW_DELAY_MSEC 1 /* msec */
struct nvgpu_pg_init pg_init;
struct nvgpu_mutex pg_mutex; /* protect pg-RPPG/MSCG enable/disable */
struct nvgpu_mutex elpg_mutex; /* protect elpg enable/disable */
int elpg_refcnt; /* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */
union {
struct pmu_perfmon_counter_v2 perfmon_counter_v2;
struct pmu_perfmon_counter_v0 perfmon_counter_v0;
};
u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM];
bool initialized;
void (*remove_support)(struct pmu_gk20a *pmu);
bool sw_ready;
bool perfmon_ready;
u32 sample_buffer;
u32 load_shadow;
u32 load_avg;
struct nvgpu_mutex isr_mutex;
bool isr_enabled;
bool zbc_ready;
union {
struct pmu_cmdline_args_v0 args_v0;
struct pmu_cmdline_args_v1 args_v1;
struct pmu_cmdline_args_v2 args_v2;
struct pmu_cmdline_args_v3 args_v3;
struct pmu_cmdline_args_v4 args_v4;
struct pmu_cmdline_args_v5 args_v5;
};
unsigned long perfmon_events_cnt;
bool perfmon_sampling_enabled;
u8 pmu_mode; /*Added for GM20b, and ACR*/
u32 falcon_id;
u32 aelpg_param[5];
u32 override_done;
struct nvgpu_firmware *fw;
};
int gk20a_init_pmu_support(struct gk20a *g);
int gk20a_init_pmu_bind_fecs(struct gk20a *g);
@@ -426,8 +138,8 @@ void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries);
int gk20a_pmu_perfmon_enable(struct gk20a *g, bool enable);
int pmu_mutex_acquire(struct pmu_gk20a *pmu, u32 id, u32 *token);
int pmu_mutex_release(struct pmu_gk20a *pmu, u32 id, u32 *token);
int pmu_mutex_acquire(struct nvgpu_pmu *pmu, u32 id, u32 *token);
int pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token);
int gk20a_pmu_destroy(struct gk20a *g);
int gk20a_pmu_load_norm(struct gk20a *g, u32 *load);
int gk20a_pmu_load_update(struct gk20a *g);
@@ -436,33 +148,33 @@ void gk20a_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles,
u32 *total_cycles);
void gk20a_init_pmu_ops(struct gpu_ops *gops);
void pmu_copy_to_dmem(struct pmu_gk20a *pmu,
void pmu_copy_to_dmem(struct nvgpu_pmu *pmu,
u32 dst, u8 *src, u32 size, u8 port);
void pmu_copy_from_dmem(struct pmu_gk20a *pmu,
void pmu_copy_from_dmem(struct nvgpu_pmu *pmu,
u32 src, u8 *dst, u32 size, u8 port);
int pmu_reset(struct pmu_gk20a *pmu);
int pmu_bootstrap(struct pmu_gk20a *pmu);
int gk20a_init_pmu(struct pmu_gk20a *pmu);
void pmu_dump_falcon_stats(struct pmu_gk20a *pmu);
void gk20a_remove_pmu_support(struct pmu_gk20a *pmu);
void pmu_seq_init(struct pmu_gk20a *pmu);
int pmu_reset(struct nvgpu_pmu *pmu);
int pmu_bootstrap(struct nvgpu_pmu *pmu);
int gk20a_init_pmu(struct nvgpu_pmu *pmu);
void pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);
void gk20a_remove_pmu_support(struct nvgpu_pmu *pmu);
void pmu_seq_init(struct nvgpu_pmu *pmu);
int gk20a_init_pmu(struct pmu_gk20a *pmu);
int gk20a_init_pmu(struct nvgpu_pmu *pmu);
int gk20a_pmu_ap_send_command(struct gk20a *g,
union pmu_ap_cmd *p_ap_cmd, bool b_block);
int gk20a_aelpg_init(struct gk20a *g);
int gk20a_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id);
void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable);
int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout_ms,
void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable);
int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms,
u32 *var, u32 val);
void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
void *param, u32 handle, u32 status);
void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
struct pmu_pg_stats_data *pg_stat_data);
int gk20a_pmu_reset(struct gk20a *g);
int pmu_idle(struct pmu_gk20a *pmu);
int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable);
int pmu_idle(struct nvgpu_pmu *pmu);
int pmu_enable_hw(struct nvgpu_pmu *pmu, bool enable);
void gk20a_pmu_surface_free(struct gk20a *g, struct nvgpu_mem *mem);
void gk20a_pmu_surface_describe(struct gk20a *g, struct nvgpu_mem *mem,
@@ -475,7 +187,7 @@ int gk20a_pmu_get_pg_stats(struct gk20a *g,
u32 pg_engine_id, struct pmu_pg_stats_data *pg_stat_data);
bool nvgpu_find_hex_in_string(char *strings, struct gk20a *g, u32 *hex_pos);
int nvgpu_pmu_perfmon_start_sampling(struct pmu_gk20a *pmu);
int nvgpu_pmu_perfmon_stop_sampling(struct pmu_gk20a *pmu);
int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu);
int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu);
#endif /*__PMU_GK20A_H__*/

19
drivers/gpu/nvgpu/gm20b/acr_gm20b.c
View File

@@ -26,6 +26,7 @@
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/acr/nvgpu_acr.h>
#include <nvgpu/firmware.h>
#include <nvgpu/pmu.h>
#include <nvgpu/linux/dma.h>
@@ -131,7 +132,7 @@ void gm20b_init_secure_pmu(struct gpu_ops *gops)
static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img)
{
struct nvgpu_firmware *pmu_fw, *pmu_desc, *pmu_sig;
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct lsf_ucode_desc *lsf_desc;
int err;
gm20b_dbg_pmu("requesting PMU ucode in GM20B\n");
@@ -382,7 +383,7 @@ int prepare_ucode_blob(struct gk20a *g)
int err;
struct ls_flcn_mgr lsfm_l, *plsfm;
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
phys_addr_t wpr_addr, wpr_page;
u32 wprsize;
int i;
@@ -470,7 +471,7 @@ static u8 lsfm_falcon_disabled(struct gk20a *g, struct ls_flcn_mgr *plsfm,
static int lsfm_discover_ucode_images(struct gk20a *g,
struct ls_flcn_mgr *plsfm)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct flcn_ucode_img ucode_img;
u32 falcon_id;
u32 i;
@@ -555,7 +556,7 @@ static int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
void *lsfm, u32 *p_bl_gen_desc_size)
{
struct wpr_carveout_info wpr_inf;
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct lsfm_managed_ucode_img *p_lsfm =
(struct lsfm_managed_ucode_img *)lsfm;
struct flcn_ucode_img *p_img = &(p_lsfm->ucode_img);
@@ -685,7 +686,7 @@ static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
struct lsfm_managed_ucode_img *pnode)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
if (pnode->wpr_header.falcon_id != pmu->falcon_id) {
gm20b_dbg_pmu("non pmu. write flcn bl gen desc\n");
g->ops.pmu.flcn_populate_bl_dmem_desc(g,
@@ -842,7 +843,7 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
u32 falcon_id, struct lsfm_managed_ucode_img *pnode)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
u32 full_app_size = 0;
u32 data = 0;
@@ -1214,7 +1215,7 @@ int acr_ucode_patch_sig(struct gk20a *g,
return 0;
}
static int bl_bootstrap(struct pmu_gk20a *pmu,
static int bl_bootstrap(struct nvgpu_pmu *pmu,
struct flcn_bl_dmem_desc *pbl_desc, u32 bl_sz)
{
struct gk20a *g = gk20a_from_pmu(pmu);
@@ -1284,7 +1285,7 @@ static int bl_bootstrap(struct pmu_gk20a *pmu,
int gm20b_init_nspmu_setup_hw1(struct gk20a *g)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
int err = 0;
gk20a_dbg_fn("");
@@ -1319,7 +1320,7 @@ static int gm20b_init_pmu_setup_hw1(struct gk20a *g,
void *desc, u32 bl_sz)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
int err;
gk20a_dbg_fn("");

9
drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
View File

@@ -15,14 +15,15 @@
#include <soc/tegra/fuse.h>
#include <nvgpu/timers.h>
#include <nvgpu/pmu.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
#include "acr_gm20b.h"
#include "pmu_gm20b.h"
#include <nvgpu/timers.h>
#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
#include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
@@ -138,7 +139,7 @@ static void pmu_handle_acr_init_wpr_msg(struct gk20a *g, struct pmu_msg *msg,
int gm20b_pmu_init_acr(struct gk20a *g)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct pmu_cmd cmd;
u32 seq;
@@ -198,7 +199,7 @@ static int pmu_gm20b_ctx_wait_lsf_ready(struct gk20a *g, u32 timeout_ms,
void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct pmu_cmd cmd;
u32 seq;

13
drivers/gpu/nvgpu/gp106/acr_gp106.c
View File

@@ -20,6 +20,7 @@
#include <nvgpu/dma.h>
#include <nvgpu/acr/nvgpu_acr.h>
#include <nvgpu/firmware.h>
#include <nvgpu/pmu.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
@@ -140,7 +141,7 @@ void gp106_init_secure_pmu(struct gpu_ops *gops)
static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
{
struct nvgpu_firmware *pmu_fw, *pmu_desc, *pmu_sig;
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct lsf_ucode_desc_v1 *lsf_desc;
int err;
@@ -382,7 +383,7 @@ static int gp106_prepare_ucode_blob(struct gk20a *g)
int err;
struct ls_flcn_mgr_v1 lsfm_l, *plsfm;
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct wpr_carveout_info wpr_inf;
if (g->acr.ucode_blob.cpu_va) {
@@ -445,7 +446,7 @@ static u8 lsfm_falcon_disabled(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
static int lsfm_discover_ucode_images(struct gk20a *g,
struct ls_flcn_mgr_v1 *plsfm)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct flcn_ucode_img_v1 ucode_img;
u32 falcon_id;
u32 i;
@@ -531,7 +532,7 @@ static int gp106_pmu_populate_loader_cfg(struct gk20a *g,
void *lsfm, u32 *p_bl_gen_desc_size)
{
struct wpr_carveout_info wpr_inf;
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct lsfm_managed_ucode_img_v2 *p_lsfm =
(struct lsfm_managed_ucode_img_v2 *)lsfm;
struct flcn_ucode_img_v1 *p_img = &(p_lsfm->ucode_img);
@@ -661,7 +662,7 @@ static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
struct lsfm_managed_ucode_img_v2 *pnode)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
if (pnode->wpr_header.falcon_id != pmu->falcon_id) {
gp106_dbg_pmu("non pmu. write flcn bl gen desc\n");
g->ops.pmu.flcn_populate_bl_dmem_desc(g,
@@ -818,7 +819,7 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
u32 falcon_id, struct lsfm_managed_ucode_img_v2 *pnode)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
u32 full_app_size = 0;
u32 data = 0;

14
drivers/gpu/nvgpu/gp106/pmu_gp106.c
View File

@@ -11,6 +11,8 @@
* more details.
*/
#include <nvgpu/pmu.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
@@ -31,7 +33,7 @@
#define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000
#define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10
static int gp106_pmu_enable_hw(struct pmu_gk20a *pmu, bool enable)
static int gp106_pmu_enable_hw(struct nvgpu_pmu *pmu, bool enable)
{
struct gk20a *g = gk20a_from_pmu(pmu);
@@ -86,7 +88,7 @@ static int gp106_pmu_enable_hw(struct pmu_gk20a *pmu, bool enable)
}
}
static int pmu_enable(struct pmu_gk20a *pmu, bool enable)
static int pmu_enable(struct nvgpu_pmu *pmu, bool enable)
{
struct gk20a *g = gk20a_from_pmu(pmu);
u32 reg_reset;
@@ -121,7 +123,7 @@ static int pmu_enable(struct pmu_gk20a *pmu, bool enable)
int gp106_pmu_reset(struct gk20a *g)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
int err = 0;
gk20a_dbg_fn("");
@@ -210,7 +212,7 @@ static void pmu_handle_param_msg(struct gk20a *g, struct pmu_msg *msg,
static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct pmu_cmd cmd;
u32 seq;
u32 status;
@@ -262,7 +264,7 @@ static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id)
void gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
struct pmu_pg_stats_data *pg_stat_data)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct pmu_pg_stats_v2 stats;
pmu_copy_from_dmem(pmu,
@@ -335,7 +337,7 @@ static bool gp106_is_priv_load(u32 falcon_id)
static void gp106_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask,
u32 flags)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct pmu_cmd cmd;
u32 seq;

12
drivers/gpu/nvgpu/gp106/sec2_gp106.c
View File

@@ -11,6 +11,8 @@
* more details.
*/
#include <nvgpu/pmu.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
@@ -88,7 +90,7 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
return completion;
}
void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
void sec2_copy_to_dmem(struct nvgpu_pmu *pmu,
u32 dst, u8 *src, u32 size, u8 port)
{
struct gk20a *g = gk20a_from_pmu(pmu);
@@ -139,7 +141,7 @@ void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
return;
}
int bl_bootstrap_sec2(struct pmu_gk20a *pmu,
int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
void *desc, u32 bl_sz)
{
struct gk20a *g = gk20a_from_pmu(pmu);
@@ -223,7 +225,7 @@ int bl_bootstrap_sec2(struct pmu_gk20a *pmu,
return 0;
}
void sec_enable_irq(struct pmu_gk20a *pmu, bool enable)
void sec_enable_irq(struct nvgpu_pmu *pmu, bool enable)
{
struct gk20a *g = gk20a_from_pmu(pmu);
@@ -281,7 +283,7 @@ void sec_enable_irq(struct pmu_gk20a *pmu, bool enable)
void init_pmu_setup_hw1(struct gk20a *g)
{
struct mm_gk20a *mm = &g->mm;
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
/* PMU TRANSCFG */
/* setup apertures - virtual */
@@ -331,7 +333,7 @@ void init_pmu_setup_hw1(struct gk20a *g)
int init_sec2_setup_hw1(struct gk20a *g,
void *desc, u32 bl_sz)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
int err;
u32 data = 0;

10
drivers/gpu/nvgpu/gp106/sec2_gp106.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -16,12 +16,12 @@
int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout);
void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
void sec2_copy_to_dmem(struct nvgpu_pmu *pmu,
u32 dst, u8 *src, u32 size, u8 port);
void sec2_dump_falcon_stats(struct pmu_gk20a *pmu);
int bl_bootstrap_sec2(struct pmu_gk20a *pmu,
void sec2_dump_falcon_stats(struct nvgpu_pmu *pmu);
int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
void *desc, u32 bl_sz);
void sec_enable_irq(struct pmu_gk20a *pmu, bool enable);
void sec_enable_irq(struct nvgpu_pmu *pmu, bool enable);
void init_pmu_setup_hw1(struct gk20a *g);
int init_sec2_setup_hw1(struct gk20a *g,
void *desc, u32 bl_sz);

13
drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
View File

@@ -15,6 +15,9 @@
#include <soc/tegra/fuse.h>
#include <nvgpu/pmu.h>
#include <nvgpu/log.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
#include "gm20b/acr_gm20b.h"
@@ -23,8 +26,6 @@
#include "pmu_gp10b.h"
#include "gp10b_sysfs.h"
#include <nvgpu/log.h>
#include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
@@ -142,7 +143,7 @@ static struct pg_init_sequence_list _pginitseq_gp10b[] = {
static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask,
u32 flags)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct pmu_cmd cmd;
u32 seq;
@@ -226,7 +227,7 @@ static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg,
int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct pmu_cmd cmd;
u32 seq;
@@ -255,7 +256,7 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
static void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
struct pmu_pg_stats_data *pg_stat_data)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
struct pmu_pg_stats_v1 stats;
pmu_copy_from_dmem(pmu,
@@ -301,7 +302,7 @@ void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr)
static int gp10b_init_pmu_setup_hw1(struct gk20a *g)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
int err;
gk20a_dbg_fn("");

328
drivers/gpu/nvgpu/include/nvgpu/pmu.h Normal file
View File

@@ -0,0 +1,328 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __NVGPU_PMU_H__
#define __NVGPU_PMU_H__
#include <nvgpu/kmem.h>
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/allocator.h>
#include <nvgpu/lock.h>
#include <nvgpu/cond.h>
#include <nvgpu/thread.h>
#include <nvgpu/nvgpu_common.h>
#include <nvgpu/flcnif_cmn.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#define nvgpu_pmu_dbg(g, fmt, args...) \
nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)
/* defined by pmu hw spec */
#define GK20A_PMU_VA_SIZE (512 * 1024 * 1024)
#define GK20A_PMU_UCODE_SIZE_MAX (256 * 1024)
#define GK20A_PMU_SEQ_BUF_SIZE 4096
#define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */
#define GK20A_PMU_DMEM_BLKSIZE2 8
#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6
#define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEAD
/* Falcon Register index */
#define PMU_FALCON_REG_R0 (0)
#define PMU_FALCON_REG_R1 (1)
#define PMU_FALCON_REG_R2 (2)
#define PMU_FALCON_REG_R3 (3)
#define PMU_FALCON_REG_R4 (4)
#define PMU_FALCON_REG_R5 (5)
#define PMU_FALCON_REG_R6 (6)
#define PMU_FALCON_REG_R7 (7)
#define PMU_FALCON_REG_R8 (8)
#define PMU_FALCON_REG_R9 (9)
#define PMU_FALCON_REG_R10 (10)
#define PMU_FALCON_REG_R11 (11)
#define PMU_FALCON_REG_R12 (12)
#define PMU_FALCON_REG_R13 (13)
#define PMU_FALCON_REG_R14 (14)
#define PMU_FALCON_REG_R15 (15)
#define PMU_FALCON_REG_IV0 (16)
#define PMU_FALCON_REG_IV1 (17)
#define PMU_FALCON_REG_UNDEFINED (18)
#define PMU_FALCON_REG_EV (19)
#define PMU_FALCON_REG_SP (20)
#define PMU_FALCON_REG_PC (21)
#define PMU_FALCON_REG_IMB (22)
#define PMU_FALCON_REG_DMB (23)
#define PMU_FALCON_REG_CSW (24)
#define PMU_FALCON_REG_CCR (25)
#define PMU_FALCON_REG_SEC (26)
#define PMU_FALCON_REG_CTX (27)
#define PMU_FALCON_REG_EXCI (28)
#define PMU_FALCON_REG_RSVD0 (29)
#define PMU_FALCON_REG_RSVD1 (30)
#define PMU_FALCON_REG_RSVD2 (31)
#define PMU_FALCON_REG_SIZE (32)
/* Choices for pmu_state */
#define PMU_STATE_OFF 0 /* PMU is off */
#define PMU_STATE_STARTING 1 /* PMU is on, but not booted */
#define PMU_STATE_INIT_RECEIVED 2 /* PMU init message received */
#define PMU_STATE_ELPG_BOOTING 3 /* PMU is booting */
#define PMU_STATE_ELPG_BOOTED 4 /* ELPG is initialized */
#define PMU_STATE_LOADING_PG_BUF 5 /* Loading PG buf */
#define PMU_STATE_LOADING_ZBC 6 /* Loading ZBC buf */
#define PMU_STATE_STARTED 7 /* Fully unitialized */
#define PMU_STATE_EXIT 8 /* Exit PMU state machine */
#define GK20A_PMU_UCODE_NB_MAX_OVERLAY 32
#define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH 64
#define PMU_MAX_NUM_SEQUENCES (256)
#define PMU_SEQ_BIT_SHIFT (5)
#define PMU_SEQ_TBL_SIZE \
(PMU_MAX_NUM_SEQUENCES >> PMU_SEQ_BIT_SHIFT)
#define PMU_INVALID_SEQ_DESC (~0)
enum {
GK20A_PMU_DMAIDX_UCODE = 0,
GK20A_PMU_DMAIDX_VIRT = 1,
GK20A_PMU_DMAIDX_PHYS_VID = 2,
GK20A_PMU_DMAIDX_PHYS_SYS_COH = 3,
GK20A_PMU_DMAIDX_PHYS_SYS_NCOH = 4,
GK20A_PMU_DMAIDX_RSVD = 5,
GK20A_PMU_DMAIDX_PELPG = 6,
GK20A_PMU_DMAIDX_END = 7
};
enum {
PMU_SEQ_STATE_FREE = 0,
PMU_SEQ_STATE_PENDING,
PMU_SEQ_STATE_USED,
PMU_SEQ_STATE_CANCELLED
};
typedef void (*pmu_callback)(struct gk20a *, struct pmu_msg *, void *, u32,
u32);
struct pmu_ucode_desc {
u32 descriptor_size;
u32 image_size;
u32 tools_version;
u32 app_version;
char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH];
u32 bootloader_start_offset;
u32 bootloader_size;
u32 bootloader_imem_offset;
u32 bootloader_entry_point;
u32 app_start_offset;
u32 app_size;
u32 app_imem_offset;
u32 app_imem_entry;
u32 app_dmem_offset;
/* Offset from appStartOffset */
u32 app_resident_code_offset;
/* Exact size of the resident code
* ( potentially contains CRC inside at the end )
*/
u32 app_resident_code_size;
/* Offset from appStartOffset */
u32 app_resident_data_offset;
/* Exact size of the resident code
* ( potentially contains CRC inside at the end )
*/
u32 app_resident_data_size;
u32 nb_overlays;
struct {u32 start; u32 size; } load_ovl[GK20A_PMU_UCODE_NB_MAX_OVERLAY];
u32 compressed;
};
struct pmu_ucode_desc_v1 {
u32 descriptor_size;
u32 image_size;
u32 tools_version;
u32 app_version;
char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH];
u32 bootloader_start_offset;
u32 bootloader_size;
u32 bootloader_imem_offset;
u32 bootloader_entry_point;
u32 app_start_offset;
u32 app_size;
u32 app_imem_offset;
u32 app_imem_entry;
u32 app_dmem_offset;
u32 app_resident_code_offset;
u32 app_resident_code_size;
u32 app_resident_data_offset;
u32 app_resident_data_size;
u32 nb_imem_overlays;
u32 nb_dmem_overlays;
struct {u32 start; u32 size; } load_ovl[64];
u32 compressed;
};
struct pmu_queue {
/* used by hw, for BIOS/SMI queue */
u32 mutex_id;
u32 mutex_lock;
/* used by sw, for LPQ/HPQ queue */
struct nvgpu_mutex mutex;
/* current write position */
u32 position;
/* physical dmem offset where this queue begins */
u32 offset;
/* logical queue identifier */
u32 id;
/* physical queue index */
u32 index;
/* in bytes */
u32 size;
/* open-flag */
u32 oflag;
bool opened; /* opened implies locked */
};
struct pmu_mutex {
u32 id;
u32 index;
u32 ref_cnt;
};
struct pmu_sequence {
u8 id;
u32 state;
u32 desc;
struct pmu_msg *msg;
union {
struct pmu_allocation_v0 in_v0;
struct pmu_allocation_v1 in_v1;
struct pmu_allocation_v2 in_v2;
struct pmu_allocation_v3 in_v3;
};
struct nvgpu_mem *in_mem;
union {
struct pmu_allocation_v0 out_v0;
struct pmu_allocation_v1 out_v1;
struct pmu_allocation_v2 out_v2;
struct pmu_allocation_v3 out_v3;
};
struct nvgpu_mem *out_mem;
u8 *out_payload;
pmu_callback callback;
void *cb_params;
};
struct nvgpu_pg_init {
bool state_change;
struct nvgpu_cond wq;
struct nvgpu_thread state_task;
};
struct nvgpu_pmu {
struct gk20a *g;
struct nvgpu_falcon *flcn;
union {
struct pmu_ucode_desc *desc;
struct pmu_ucode_desc_v1 *desc_v1;
};
struct nvgpu_mem ucode;
struct nvgpu_mem pg_buf;
/* TBD: remove this if ZBC seq is fixed */
struct nvgpu_mem seq_buf;
struct nvgpu_mem trace_buf;
struct nvgpu_mem wpr_buf;
bool buf_loaded;
struct pmu_sha1_gid gid_info;
struct pmu_queue queue[PMU_QUEUE_COUNT];
struct pmu_sequence *seq;
unsigned long pmu_seq_tbl[PMU_SEQ_TBL_SIZE];
u32 next_seq_desc;
struct pmu_mutex *mutex;
u32 mutex_cnt;
struct nvgpu_mutex pmu_copy_lock;
struct nvgpu_mutex pmu_seq_lock;
struct nvgpu_allocator dmem;
u32 *ucode_image;
bool pmu_ready;
u32 zbc_save_done;
u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE];
u32 elpg_stat;
u32 mscg_stat;
u32 mscg_transition_state;
int pmu_state;
#define PMU_ELPG_ENABLE_ALLOW_DELAY_MSEC 1 /* msec */
struct nvgpu_pg_init pg_init;
struct nvgpu_mutex pg_mutex; /* protect pg-RPPG/MSCG enable/disable */
struct nvgpu_mutex elpg_mutex; /* protect elpg enable/disable */
/* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */
int elpg_refcnt;
union {
struct pmu_perfmon_counter_v2 perfmon_counter_v2;
struct pmu_perfmon_counter_v0 perfmon_counter_v0;
};
u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM];
bool initialized;
void (*remove_support)(struct nvgpu_pmu *pmu);
bool sw_ready;
bool perfmon_ready;
u32 sample_buffer;
u32 load_shadow;
u32 load_avg;
struct nvgpu_mutex isr_mutex;
bool isr_enabled;
bool zbc_ready;
union {
struct pmu_cmdline_args_v0 args_v0;
struct pmu_cmdline_args_v1 args_v1;
struct pmu_cmdline_args_v2 args_v2;
struct pmu_cmdline_args_v3 args_v3;
struct pmu_cmdline_args_v4 args_v4;
struct pmu_cmdline_args_v5 args_v5;
};
unsigned long perfmon_events_cnt;
bool perfmon_sampling_enabled;
u8 pmu_mode; /*Added for GM20b, and ACR*/
u32 falcon_id;
u32 aelpg_param[5];
u32 override_done;
struct nvgpu_firmware *fw;
};
#endif /* __NVGPU_PMU_H__ */

13
drivers/gpu/nvgpu/lpwr/lpwr.c
View File

@@ -12,10 +12,9 @@
*/
#include <nvgpu/bios.h>
#include <nvgpu/pmu.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
#include "gp106/pmu_gp106.h"
#include "gm206/bios_gm206.h"
#include "pstate/pstate.h"
#include "perf/perf.h"
@@ -207,7 +206,7 @@ static void nvgpu_pmu_handle_param_lpwr_msg(struct gk20a *g,
*ack_status = 1;
gp106_dbg_pmu("lpwr-param is acknowledged from PMU %x",
nvgpu_pmu_dbg(g, "lpwr-param is acknowledged from PMU %x",
msg->msg.pg.msg_type);
}
@@ -243,7 +242,7 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
PMU_PG_PARAM_CMD_MCLK_CHANGE;
cmd.cmd.pg.mclk_change.data = payload;
gp106_dbg_pmu("cmd post MS PMU_PG_PARAM_CMD_MCLK_CHANGE");
nvgpu_pmu_dbg(g, "cmd post MS PMU_PG_PARAM_CMD_MCLK_CHANGE");
status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL,
PMU_COMMAND_QUEUE_HPQ,
nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0);
@@ -276,7 +275,7 @@ u32 nvgpu_lpwr_post_init(struct gk20a *g)
cmd.cmd.pg.post_init.cmd_id =
PMU_PG_PARAM_CMD_POST_INIT;
gp106_dbg_pmu("cmd post post-init PMU_PG_PARAM_CMD_POST_INIT");
nvgpu_pmu_dbg(g, "cmd post post-init PMU_PG_PARAM_CMD_POST_INIT");
status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL,
PMU_COMMAND_QUEUE_LPQ,
nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0);
@@ -336,7 +335,7 @@ u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num)
int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
u32 status = 0;
u32 is_mscg_supported = 0;
u32 is_rppg_supported = 0;
@@ -376,7 +375,7 @@ int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock)
int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock)
{
struct pmu_gk20a *pmu = &g->pmu;
struct nvgpu_pmu *pmu = &g->pmu;
int status = 0;
u32 is_mscg_supported = 0;
u32 is_rppg_supported = 0;

8
drivers/gpu/nvgpu/lpwr/rppg.c
View File

@@ -11,9 +11,9 @@
* more details.
*/
#include <nvgpu/pmu.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
#include "gp106/pmu_gp106.h"
#include "gm206/bios_gm206.h"
#include "pstate/pstate.h"
@@ -29,13 +29,13 @@ static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg,
case NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK:
ctrlId = msg->msg.pg.rppg_msg.init_ctrl_ack.ctrl_id;
*success = 1;
gp106_dbg_pmu("RPPG is acknowledged from PMU %x",
nvgpu_pmu_dbg(g, "RPPG is acknowledged from PMU %x",
msg->msg.pg.msg_type);
break;
}
}
gp106_dbg_pmu("RPPG is acknowledged from PMU %x",
nvgpu_pmu_dbg(g, "RPPG is acknowledged from PMU %x",
msg->msg.pg.msg_type);
}

6
drivers/gpu/nvgpu/perf/perf.c
View File

@@ -11,13 +11,13 @@
* more details.
*/
#include <nvgpu/bug.h>
#include <nvgpu/pmu.h>
#include "gk20a/gk20a.h"
#include "perf.h"
#include "gk20a/pmu_gk20a.h"
#include "clk/clk_arb.h"
#include <nvgpu/bug.h>
struct perfrpc_pmucmdhandler_params {
struct nv_pmu_perf_rpc *prpccall;
u32 success;

1
drivers/gpu/nvgpu/perf/vfe_equ.c
View File

@@ -20,7 +20,6 @@
#include "boardobj/boardobjgrp_e255.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
static struct vfe_equ *construct_vfe_equ(struct gk20a *g, void *pargs);
static u32 devinit_get_vfe_equ_table(struct gk20a *g,

1
drivers/gpu/nvgpu/perf/vfe_var.c
View File

@@ -20,7 +20,6 @@
#include "boardobj/boardobjgrp_e32.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
static u32 devinit_get_vfe_var_table(struct gk20a *g,
struct vfe_vars *pvarobjs);

2
drivers/gpu/nvgpu/pmgr/pmgrpmu.c
View File

@@ -13,11 +13,11 @@
#include <nvgpu/kmem.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include <nvgpu/pmu.h>
#include "gk20a/gk20a.h"
#include "gk20a/platform_gk20a.h"
#include "gm206/bios_gm206.h"
#include "gk20a/pmu_gk20a.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"

1
drivers/gpu/nvgpu/pmgr/pwrdev.c
View File

@@ -18,7 +18,6 @@
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "gk20a/pmu_gk20a.h"
static u32 _pwr_device_pmudata_instget(struct gk20a *g,
struct nv_pmu_boardobjgrp *pmuboardobjgrp,

1
drivers/gpu/nvgpu/pmgr/pwrmonitor.c
View File

@@ -18,7 +18,6 @@
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "gk20a/pmu_gk20a.h"
static u32 _pwr_channel_pmudata_instget(struct gk20a *g,
struct nv_pmu_boardobjgrp *pmuboardobjgrp,

1
drivers/gpu/nvgpu/pmgr/pwrpolicy.c
View File

@@ -20,7 +20,6 @@
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "gk20a/pmu_gk20a.h"
#define _pwr_policy_limitarboutputget_helper(p_limit_arb) (p_limit_arb)->output
#define _pwr_policy_limitdeltaapply(limit, delta) ((u32)max(((s32)limit) + (delta), 0))

3
drivers/gpu/nvgpu/therm/thrmchannel.c
View File

@@ -12,14 +12,13 @@
*/
#include <nvgpu/bios.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "gk20a/gk20a.h"
#include "thrmchannel.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "gm206/bios_gm206.h"
#include "gk20a/pmu_gk20a.h"
static u32 _therm_channel_pmudatainit_device(struct gk20a *g,
struct boardobj *board_obj_ptr,

3
drivers/gpu/nvgpu/therm/thrmdev.c
View File

@@ -12,14 +12,13 @@
*/
#include <nvgpu/bios.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "gk20a/gk20a.h"
#include "thrmdev.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "gm206/bios_gm206.h"
#include "gk20a/pmu_gk20a.h"
#include "ctrl/ctrltherm.h"
static struct boardobj *construct_therm_device(struct gk20a *g,

1
drivers/gpu/nvgpu/volt/volt_dev.c
View File

@@ -17,7 +17,6 @@
#include <nvgpu/kmem.h>
#include "gk20a/gk20a.h"
#include "gk20a/pmu_gk20a.h"
#include "gm206/bios_gm206.h"
#include "boardobj/boardobjgrp.h"

5
drivers/gpu/nvgpu/volt/volt_pmu.c
View File

@@ -11,16 +11,17 @@
* more details.
*/
#include <nvgpu/pmu.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include "gk20a/gk20a.h"
#include "boardobj/boardobjgrp.h"
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "ctrl/ctrlvolt.h"
#include "ctrl/ctrlperf.h"
#include "gk20a/pmu_gk20a.h"
#include "volt.h"
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#define RAIL_COUNT 2

1
drivers/gpu/nvgpu/volt/volt_policy.c
View File

@@ -18,7 +18,6 @@
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
#include "volt.h"

1
drivers/gpu/nvgpu/volt/volt_rail.c
View File

@@ -18,7 +18,6 @@
#include "boardobj/boardobjgrp_e32.h"
#include "gm206/bios_gm206.h"
#include "ctrl/ctrlvolt.h"
#include "gk20a/pmu_gk20a.h"
#include "volt.h"