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gpu: nvgpu: unit: coverage for gm20b pbdma status
Add coverage for the following function: - gm20b_read_pbdma_status_info Jira NVGPU-4673 Change-Id: I30c20932f84aac4a96efcb023ca85c5fbaecac1c Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2270924 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
committed by
Alex Waterman
Alex Waterman
parent
11aeb94d75
commit
6828487f70
@@ -1,4 +1,4 @@
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# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a
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# copy of this software and associated documentation files (the "Software"),
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@@ -20,7 +20,7 @@
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.SUFFIXES:
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OBJS = nvgpu-pbdma-gm20b.o
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OBJS = nvgpu-pbdma-gm20b.o nvgpu-pbdma-status-gm20b.o
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MODULE = nvgpu-pbdma-gm20b
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LIB_PATHS += -lnvgpu-fifo-common
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@@ -1,6 +1,6 @@
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################################### tell Emacs this is a -*- makefile-gmake -*-
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#
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# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a
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# copy of this software and associated documentation files (the "Software"),
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@@ -25,7 +25,7 @@
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###############################################################################
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NVGPU_UNIT_NAME = nvgpu-pbdma-gm20b
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NVGPU_UNIT_SRCS = nvgpu-pbdma-gm20b.c
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NVGPU_UNIT_SRCS = nvgpu-pbdma-gm20b.c nvgpu-pbdma-status-gm20b.c
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NVGPU_UNIT_INTERFACE_DIRS := \
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$(NV_SOURCE)/kernel/nvgpu/userspace/units/fifo \
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -43,6 +43,7 @@
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#include "../../nvgpu-fifo-common.h"
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#include "../../nvgpu-fifo-gv11b.h"
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#include "nvgpu-pbdma-gm20b.h"
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#include "nvgpu-pbdma-status-gm20b.h"
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#ifdef PBDMA_GM20B_UNIT_DEBUG
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#undef unit_verbose
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@@ -547,6 +548,9 @@ struct unit_module_test nvgpu_pbdma_gm20b_tests[] = {
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UNIT_TEST(pbdma_get_fc_subdevice, test_gm20b_pbdma_get_fc_subdevice, NULL, 0),
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UNIT_TEST(pbdma_get_ctrl_hce_priv_mode_yes, test_gm20b_pbdma_get_ctrl_hce_priv_mode_yes, NULL, 0),
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UNIT_TEST(pbdma_get_userd, test_gm20b_pbdma_get_userd, NULL, 0),
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/* pbdma status */
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UNIT_TEST(read_pbdma_status_info, test_gm20b_read_pbdma_status_info, NULL, 0),
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UNIT_TEST(remove_support, test_fifo_remove_support, NULL, 0),
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};
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169
userspace/units/fifo/pbdma/gm20b/nvgpu-pbdma-status-gm20b.c
Normal file
169
userspace/units/fifo/pbdma/gm20b/nvgpu-pbdma-status-gm20b.c
Normal file
@@ -0,0 +1,169 @@
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/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <stdlib.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include <unit/io.h>
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#include <unit/unit.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/tsg.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/pbdma.h>
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#include <nvgpu/pbdma_status.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/io.h>
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#include "hal/fifo/pbdma_status_gm20b.h"
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#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
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#include "../../nvgpu-fifo-common.h"
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#include "../../nvgpu-fifo-gv11b.h"
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#include "nvgpu-pbdma-status-gm20b.h"
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#ifdef PBDMA_STATUS_GM20B_UNIT_DEBUG
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#undef unit_verbose
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#define unit_verbose unit_info
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#else
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#define unit_verbose(unit, msg, ...) \
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do { \
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if (0) { \
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unit_info(unit, msg, ##__VA_ARGS__); \
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} \
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} while (0)
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#endif
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#define F_PBDMA_INFO_CTX_IS_TSG BIT(0)
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#define F_PBDMA_INFO_NEXT_CTX_IS_TSG BIT(1)
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#define F_PBDMA_INFO_LAST BIT(2)
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#define NUM_PBDMA_STATUS_CHAN 5
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int test_gm20b_read_pbdma_status_info(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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int ret = UNIT_FAIL;
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const int pbdma_id = 0;
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u32 pbdma_reg_status = 0;
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u32 id = 1;
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u32 next_id = 5;
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u32 id_type;
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u32 next_id_type;
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struct nvgpu_pbdma_status_info status;
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u32 i;
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u32 branches = 0;
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int pbdma_status_chan[NUM_PBDMA_STATUS_CHAN] = {
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fifo_pbdma_status_chan_status_valid_v(),
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fifo_pbdma_status_chan_status_chsw_load_v(),
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fifo_pbdma_status_chan_status_chsw_save_v(),
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fifo_pbdma_status_chan_status_chsw_switch_v(),
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2 /* invalid */
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};
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u32 expected_chsw_status[NUM_PBDMA_STATUS_CHAN] = {
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NVGPU_PBDMA_CHSW_STATUS_VALID,
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NVGPU_PBDMA_CHSW_STATUS_LOAD,
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NVGPU_PBDMA_CHSW_STATUS_SAVE,
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NVGPU_PBDMA_CHSW_STATUS_SWITCH,
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NVGPU_PBDMA_CHSW_STATUS_INVALID
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};
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bool id_valid;
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bool next_id_valid;
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for (i = 0; i < NUM_PBDMA_STATUS_CHAN; i++) {
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id = (id + 1) & 0xfff;
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next_id = (next_id + 1) & 0xfff;
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id_valid =
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((pbdma_status_chan[i] == fifo_pbdma_status_chan_status_valid_v()) ||
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(pbdma_status_chan[i] == fifo_pbdma_status_chan_status_chsw_save_v()) ||
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(pbdma_status_chan[i] == fifo_pbdma_status_chan_status_chsw_switch_v()));
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next_id_valid =
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((pbdma_status_chan[i] == fifo_pbdma_status_chan_status_chsw_load_v()) ||
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(pbdma_status_chan[i] == fifo_pbdma_status_chan_status_chsw_switch_v()));
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for (branches = 0; branches < F_PBDMA_INFO_LAST; branches++) {
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id_type = branches & F_PBDMA_INFO_CTX_IS_TSG ?
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fifo_pbdma_status_id_type_tsgid_v() :
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fifo_pbdma_status_id_type_chid_v();
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next_id_type = branches & F_PBDMA_INFO_NEXT_CTX_IS_TSG ?
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fifo_pbdma_status_next_id_type_tsgid_v() :
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fifo_pbdma_status_next_id_type_chid_v();
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pbdma_reg_status =
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(pbdma_status_chan[i] << 13) |
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(id << 0) |
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(id_type << 12) |
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(next_id << 16) |
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(next_id_type << 28);
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nvgpu_writel(g, fifo_pbdma_status_r(pbdma_id),
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pbdma_reg_status);
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gm20b_read_pbdma_status_info(g, pbdma_id, &status);
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unit_assert(status.pbdma_reg_status == pbdma_reg_status,
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goto done);
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unit_assert(status.chsw_status == expected_chsw_status[i],
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goto done);
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if (id_valid) {
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unit_assert(status.id == id, goto done);
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unit_assert(status.id_type == id_type, goto done);
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} else {
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unit_assert(status.id == PBDMA_STATUS_ID_INVALID,
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goto done);
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unit_assert(status.id_type ==
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PBDMA_STATUS_ID_TYPE_INVALID, goto done);
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}
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if (next_id_valid) {
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unit_assert(status.next_id == next_id, goto done);
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unit_assert(status.next_id_type == next_id_type,
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goto done);
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} else {
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unit_assert(status.next_id ==
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PBDMA_STATUS_NEXT_ID_INVALID, goto done);
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unit_assert(status.next_id_type ==
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PBDMA_STATUS_NEXT_ID_TYPE_INVALID, goto done);
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}
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}
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}
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ret = UNIT_SUCCESS;
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done:
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if (ret != UNIT_SUCCESS) {
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unit_err(m, "%s i=%u branches=%08x\n", __func__, i, branches);
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}
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return ret;
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}
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67
userspace/units/fifo/pbdma/gm20b/nvgpu-pbdma-status-gm20b.h
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67
userspace/units/fifo/pbdma/gm20b/nvgpu-pbdma-status-gm20b.h
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@@ -0,0 +1,67 @@
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/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef UNIT_NVGPU_PBDMA_STATUS_GM20B_H
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#define UNIT_NVGPU_PBDMA_STATUS_GM20B_H
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#include <nvgpu/types.h>
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struct unit_module;
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struct gk20a;
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/** @addtogroup SWUTS-fifo-pbdma-status-gm20b
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* @{
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*
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* Software Unit Test Specification for fifo/pbdma/gm20b
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*/
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/**
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* Test specification for: test_gm20b_read_pbdma_status_info
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*
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* Description: Branch coverage for read PBDMA status.
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*
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* Test Type: Feature, Branch coverage.
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*
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* Targets: gm20b_read_pbdma_status_info
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*
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* Input: test_fifo_init_support() run for this GPU
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*
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* Steps:
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* - Set fifo_pbdma_status_r with a combination of:
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* - chsw status (valid, load, save, switch and invalid).
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* - id and id_type (tsg/ch).
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* - next_id and next_id_type (tsg/ch).
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* - Call gm20b_read_pbdma_status_info.
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* - Check that pbdma_reg_status is set value read from fifo_pbdma_status_r.
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* - Check that chsw_status is consistent with register value.
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* - Check that id/id_type and next_id/next_id_type are consistent
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* (depending on chsw_status).
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_gm20b_read_pbdma_status_info(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* @}
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*/
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#endif /* UNIT_NVGPU_PBDMA_STATUS_GM20B_H */
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