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gpu: nvgpu: remove Dynamic TPC-PG code
- Dynamic TPC-PG feature is not fully implemented and these variables are not using anywhere, so removing this code. JIRA NVGPU-5849 Change-Id: I4949e991a62e06f4aff10c3fbe7516546e49f55e Signed-off-by: Seeta Rama Raju <srajum@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2544789 (cherry picked from commit bb28c7d8bfd873283b24e8a1812e23c554cc6c18) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551208 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -173,19 +173,6 @@ struct nvgpu_tsg {
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* the TSG.
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* the TSG.
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*/
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*/
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pid_t tgid;
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pid_t tgid;
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/**
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* Number of active TPCs as requested by userspace.
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* This is used while requesting for dynamic TPC PG (power gating).
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* TPC PG is specific to chip.
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*/
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u32 num_active_tpcs;
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/** Set to true if dynamic TPC PG is requested to be enabled. */
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bool tpc_pg_enabled;
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/**
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* Set to true if dynamic TPC PG is enabled and #num_active_tpcs is
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* non-zero.
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*/
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bool tpc_num_initialized;
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/**
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/**
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* Set to true if tsgid is acquired else set to false.
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* Set to true if tsgid is acquired else set to false.
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* This is protected by #nvgpu_fifo.tsg_inuse_mutex. Acquire/Release
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* This is protected by #nvgpu_fifo.tsg_inuse_mutex. Acquire/Release
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@@ -93,7 +93,6 @@ static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g,
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struct nvgpu_tsg *tsg = priv->tsg;
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struct nvgpu_tsg *tsg = priv->tsg;
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struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
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struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
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struct nvgpu_channel *ch;
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struct nvgpu_channel *ch;
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struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
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u32 max_subctx_count;
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u32 max_subctx_count;
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u32 gpu_instance_id;
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u32 gpu_instance_id;
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int err = 0;
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int err = 0;
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@@ -117,21 +116,6 @@ static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g,
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goto idle;
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goto idle;
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}
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}
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if (arg->tpc_pg_enabled && (!tsg->tpc_num_initialized)) {
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if ((arg->num_active_tpcs >
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nvgpu_gr_config_get_max_tpc_count(gr_config)) ||
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!(arg->num_active_tpcs)) {
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nvgpu_err(g, "Invalid num of active TPCs");
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err = -EINVAL;
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goto ch_put;
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}
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tsg->tpc_num_initialized = true;
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tsg->num_active_tpcs = arg->num_active_tpcs;
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tsg->tpc_pg_enabled = true;
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} else {
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tsg->tpc_pg_enabled = false; nvgpu_log(g, gpu_dbg_info, "dynamic TPC-PG not enabled");
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}
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gpu_instance_id = nvgpu_get_gpu_instance_id_from_cdev(g, priv->cdev);
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gpu_instance_id = nvgpu_get_gpu_instance_id_from_cdev(g, priv->cdev);
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nvgpu_assert(gpu_instance_id < g->mig.num_gpu_instances);
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nvgpu_assert(gpu_instance_id < g->mig.num_gpu_instances);
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@@ -35,9 +35,7 @@ struct nvgpu_tsg_bind_channel_ex_args {
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/* in: VEID in Volta */
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/* in: VEID in Volta */
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__u32 subcontext_id;
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__u32 subcontext_id;
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__u32 num_active_tpcs;
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__u8 reserved[16];
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__u8 tpc_pg_enabled;
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__u8 reserved[11];
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};
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};
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/*
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/*
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