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gpu: nvgpu: unit: fix falcon dmemc read logic

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Falcon DMEMC register read returns the bytes copied to DMEM. There was
a mistake in calculating the bytes and setting access->value properly
in falcon utf register read function. Fix it.

JIRA NVGPU-2220

Change-Id: If6ba03f734e27d8d0d027f873b56330c17f7aa0b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201515
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-09-19 16:19:44 +05:30
committed by Alex Waterman
parent 7ee71a4f4b
commit 69f990623b
1 changed files with 1 additions and 2 deletions
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3
userspace/units/falcon/falcon_utf.c
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@@ -122,8 +122,7 @@ void nvgpu_utf_falcon_readl_access_reg_fn(struct gk20a *g,
ctrl_r = nvgpu_posix_io_readl_reg_space(g, ctrl_r = nvgpu_posix_io_readl_reg_space(g,
flcn_base + falcon_falcon_dmemc_r(0)); flcn_base + falcon_falcon_dmemc_r(0));
offset = access->value & addr_mask; access->value = ctrl_r & addr_mask;
access->value = offset * 4U;
} else { } else {
access->value = nvgpu_posix_io_readl_reg_space(g, access->addr); access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
} }