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gpu: nvgpu: Create common.pmu.clk.vf_point unit

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This patch does the following.
1. Append public functions with nvgpu.
2. Move public functions & structure to include/pmu/clk.
3. Remove inclusion of HW header files in common.
4. Move FREQ_STEP_SIZE_MHZ to clk_prog.h as it is used there.
5. Fix 16.3 and 11.3 Misra Violations.

Jira NVGPU-1965

Change-Id: I268d257d6de9c986e456a666cf6d633fe10fc440
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2024992
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Abdul Salam
2019-02-25 17:44:25 +05:30
committed by mobile promotions
parent 56f9753188
commit 6a6c2ec0b0
10 changed files with 74 additions and 108 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/common/pmu/clk/clk.c
View File

@@ -30,6 +30,7 @@
#include <nvgpu/pmu/pstate.h>
#include <nvgpu/pmu/volt.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/clk/clk_vf_point.h>
#include "clk.h"
#include <nvgpu/timers.h>
@@ -902,7 +903,7 @@ int nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g)
u32 gpcclk_voltuv = 0;
u32 voltuv = 0;
status = clk_vf_point_cache(g);
status = nvgpu_clk_vf_point_cache(g);
if (status != 0) {
nvgpu_err(g,"caching failed");
return status;
@@ -950,7 +951,7 @@ int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g)
u32 gpcclk_voltuv = 0U;
u32 voltuv = 0U;
status = clk_vf_point_cache(g);
status = nvgpu_clk_vf_point_cache(g);
if (status != 0) {
nvgpu_err(g, "caching failed");
return status;

1
drivers/gpu/nvgpu/common/pmu/clk/clk.h
View File

@@ -30,7 +30,6 @@
#include "clk_fll.h"
#include "clk_domain.h"
#include "clk_prog.h"
#include "clk_vf_point.h"
#include "clk_mclk.h"
#include "clk_freq_controller.h"
#include "clk_freq_domain.h"

4
drivers/gpu/nvgpu/common/pmu/clk/clk_arb.c
View File

@@ -37,9 +37,9 @@
#include <nvgpu/pmu/volt.h>
#include <nvgpu/pmu/lpwr.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/clk/clk_vf_point.h>
#include "clk.h"
#include "clk_vf_point.h"
int nvgpu_clk_notification_queue_alloc(struct gk20a *g,
struct nvgpu_clk_notification_queue *queue,
@@ -235,7 +235,7 @@ static void nvgpu_clk_arb_run_vf_table_cb(struct nvgpu_clk_arb *arb)
int err;
/* get latest vf curve from pmu */
err = clk_vf_point_cache(g);
err = nvgpu_clk_vf_point_cache(g);
if (err != 0) {
nvgpu_err(g, "failed to cache VF table");
nvgpu_clk_arb_set_global_alarm(g,

4
drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c
View File

@@ -31,8 +31,6 @@
#include "clk.h"
#include "clk_prog.h"
#include "clk_vf_point.h"
#include "gp106/bios_gp106.h"
static struct clk_prog *construct_clk_prog(struct gk20a *g, void *pargs);
static int devinit_get_clk_prog_table(struct gk20a *g,
@@ -923,7 +921,7 @@ static int _clk_prog_1x_master_rail_construct_vf_point(struct gk20a *g,
nvgpu_log_info(g, " ");
p_vf_point = construct_clk_vf_point(g, (void *)p_vf_point_tmp);
p_vf_point = nvgpu_construct_clk_vf_point(g, (void *)p_vf_point_tmp);
if (p_vf_point == NULL) {
status = -ENOMEM;
goto done;

1
drivers/gpu/nvgpu/common/pmu/clk/clk_prog.h
View File

@@ -31,6 +31,7 @@
#include <nvgpu/boardobjgrpmask.h>
struct clk_prog_1x_master;
#define FREQ_STEP_SIZE_MHZ 15U
typedef int vf_flatten(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
struct clk_prog_1x_master *p1xmaster,

14
drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c
View File

@@ -32,7 +32,6 @@
#include <nvgpu/pmu/perf.h>
#include "clk.h"
#include "clk_vf_point.h"
static int _clk_vf_point_pmudatainit_super(struct gk20a *g, struct boardobj
*board_obj_ptr, struct nv_pmu_boardobj *ppmudata);
@@ -369,7 +368,7 @@ static int clk_vf_point_construct_freq_35(struct gk20a *g,
return status;
}
struct clk_vf_point *construct_clk_vf_point(struct gk20a *g, void *pargs)
struct clk_vf_point *nvgpu_construct_clk_vf_point(struct gk20a *g, void *pargs)
{
struct boardobj *board_obj_ptr = NULL;
int status;
@@ -397,7 +396,8 @@ struct clk_vf_point *construct_clk_vf_point(struct gk20a *g, void *pargs)
break;
default:
return NULL;
status = -EINVAL;
break;
}
if (status != 0) {
@@ -406,7 +406,7 @@ struct clk_vf_point *construct_clk_vf_point(struct gk20a *g, void *pargs)
nvgpu_log_info(g, " Done");
return (struct clk_vf_point *)board_obj_ptr;
return (struct clk_vf_point *)(void *)board_obj_ptr;
}
static int _clk_vf_point_pmudatainit_super(struct gk20a *g,
@@ -708,7 +708,7 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq
}
/*get latest vf point data from PMU */
int clk_vf_point_cache(struct gk20a *g)
int nvgpu_clk_vf_point_cache(struct gk20a *g)
{
struct nvgpu_clk_vf_points *pclk_vf_points;
@@ -739,14 +739,14 @@ int clk_vf_point_cache(struct gk20a *g)
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
status = pboardobjgrp->pmustatusinstget(g,
(struct nv_pmu_boardobjgrp *)pboardobjgrppmu,
(struct nv_pmu_boardobjgrp *)(void *)pboardobjgrppmu,
&pboardobjpmustatus, index);
if (status != 0) {
nvgpu_err(g, "could not get status object instance");
return status;
}
status = clk_vf_point_update(g, pboardobj,
(struct nv_pmu_boardobj *)pboardobjpmustatus);
(struct nv_pmu_boardobj *)(void *)pboardobjpmustatus);
if (status != 0) {
nvgpu_err(g, "invalid data from pmu at %d", index);
return status;

92
drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.h
View File

@@ -1,92 +0,0 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_CLK_VF_POINT_H
#define NVGPU_CLK_VF_POINT_H
#include <nvgpu/pmuif/ctrlclk.h>
#include <nvgpu/pmuif/ctrlboardobj.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/boardobjgrp_e255.h>
#include <nvgpu/boardobjgrpmask.h>
#define VMIN_PAD_UV 50000U
#define FREQ_STEP_SIZE_MHZ 15U
int clk_vf_point_cache(struct gk20a *g);
struct nvgpu_clk_arb;
struct nvgpu_clk_slave_freq{
u16 gpc_mhz;
u16 sys_mhz;
u16 xbar_mhz;
u16 host_mhz;
u16 nvd_mhz;
};
int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq *vf_point);
int nvgpu_clk_arb_find_slave_points(struct nvgpu_clk_arb *arb,struct nvgpu_clk_slave_freq *vf_point);
struct clk_vf_point {
struct boardobj super;
u8 vfe_equ_idx;
u8 volt_rail_idx;
struct ctrl_clk_vf_pair pair;
};
struct clk_vf_point_volt {
struct clk_vf_point super;
u32 source_voltage_uv;
struct ctrl_clk_freq_delta freq_delta;
};
struct clk_vf_point_freq {
struct clk_vf_point super;
int volt_delta_uv;
};
#define CLK_CLK_VF_POINT_GET(pclk, idx) \
((struct clk_vf_point *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
&pclk->clk_vf_pointobjs.super.super, (u8)(idx)))
#define clkvfpointpairget(pvfpoint) \
(&((pvfpoint)->pair))
#define clkvfpointfreqmhzget(pgpu, pvfpoint) \
CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(clkvfpointpairget(pvfpoint))
#define clkvfpointfreqdeltamhzGet(pgpu, pvfPoint) \
((BOARDOBJ_GET_TYPE(pvfpoint) == CTRL_CLK_CLK_VF_POINT_TYPE_VOLT) ? \
(((struct clk_vf_point_volt *)(pvfpoint))->freq_delta_khz / 1000) : 0)
#define clkvfpointfreqmhzset(pgpu, pvfpoint, _freqmhz) \
CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(clkvfpointpairget(pvfpoint), _freqmhz)
#define clkvfpointvoltageuvset(pgpu, pvfpoint, _voltageuv) \
CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(clkvfpointpairget(pvfpoint), \
_voltageuv)
#define clkvfpointvoltageuvget(pgpu, pvfpoint) \
CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(clkvfpointpairget(pvfpoint)) \
struct clk_vf_point *construct_clk_vf_point(struct gk20a *g, void *pargs);
#endif /* NVGPU_CLK_VF_POINT_H */

1
drivers/gpu/nvgpu/common/pmu/pmu_fw.c
View File

@@ -33,6 +33,7 @@
#include <nvgpu/pmu/pstate.h>
#include <nvgpu/pmu/volt.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/clk/clk_vf_point.h>
/* PMU NS UCODE IMG */
#define NVGPU_PMU_NS_UCODE_IMAGE "gpmu_ucode.bin"

3
drivers/gpu/nvgpu/gv100/clk_arb_gv100.c
View File

@@ -24,6 +24,7 @@
#include <nvgpu/clk_arb.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/timers.h>
#include <nvgpu/pmu/clk/clk_vf_point.h>
#include "clk_arb_gv100.h"
#include "common/pmu/clk/clk.h"
@@ -248,7 +249,7 @@ int gv100_init_clk_arbiter(struct gk20a *g)
arb->debugfs_set = true;
}
#endif
err = clk_vf_point_cache(g);
err = nvgpu_clk_vf_point_cache(g);
if (err < 0) {
goto init_fail;
}

57
drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vf_point.h
View File

@@ -36,6 +36,56 @@ struct nvgpu_clk_vf_points {
struct boardobjgrp_e255 super;
};
struct nvgpu_clk_slave_freq{
u16 gpc_mhz;
u16 sys_mhz;
u16 xbar_mhz;
u16 host_mhz;
u16 nvd_mhz;
};
struct clk_vf_point {
struct boardobj super;
u8 vfe_equ_idx;
u8 volt_rail_idx;
struct ctrl_clk_vf_pair pair;
};
struct clk_vf_point_volt {
struct clk_vf_point super;
u32 source_voltage_uv;
struct ctrl_clk_freq_delta freq_delta;
};
struct clk_vf_point_freq {
struct clk_vf_point super;
int volt_delta_uv;
};
#define CLK_CLK_VF_POINT_GET(pclk, idx) \
((struct clk_vf_point *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
&pclk->clk_vf_pointobjs.super.super, (u8)(idx)))
#define clkvfpointpairget(pvfpoint) \
(&((pvfpoint)->pair))
#define clkvfpointfreqmhzget(pgpu, pvfpoint) \
CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(clkvfpointpairget(pvfpoint))
#define clkvfpointfreqdeltamhzGet(pgpu, pvfPoint) \
((BOARDOBJ_GET_TYPE(pvfpoint) == CTRL_CLK_CLK_VF_POINT_TYPE_VOLT) ? \
(((struct clk_vf_point_volt *)(pvfpoint))->freq_delta_khz / 1000) : 0)
#define clkvfpointfreqmhzset(pgpu, pvfpoint, _freqmhz) \
CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(clkvfpointpairget(pvfpoint), _freqmhz)
#define clkvfpointvoltageuvset(pgpu, pvfpoint, _voltageuv) \
CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(clkvfpointpairget(pvfpoint), \
_voltageuv)
#define clkvfpointvoltageuvget(pgpu, pvfpoint) \
CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(clkvfpointpairget(pvfpoint)) \
u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g,
struct nv_pmu_clk_rpc *rpccall,
struct nvgpu_set_fll_clk *setfllclk);
@@ -44,5 +94,12 @@ u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
struct nvgpu_set_fll_clk *setfllclk);
int nvgpu_clk_vf_point_sw_setup(struct gk20a *g);
int nvgpu_clk_vf_point_pmu_setup(struct gk20a *g);
struct clk_vf_point *nvgpu_construct_clk_vf_point(struct gk20a *g,
void *pargs);
int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g,
struct nvgpu_clk_slave_freq *vf_point);
int nvgpu_clk_arb_find_slave_points(struct nvgpu_clk_arb *arb,
struct nvgpu_clk_slave_freq *vf_point);
int nvgpu_clk_vf_point_cache(struct gk20a *g);
#endif /* NVGPU_PMU_CLK_VF_POINT_H */