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gpu: nvgpu: unit: add UT for gops.gr.init.commit_global_bundle_cb

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Add a code coverage test for HAL function exposed by common.gr.init
subunit :
g->ops.gr.init.commit_global_bundle_cb

Jira NVGPU-4778

Change-Id: Ibd8bd8513c63e6d5a6734a4ccc6744861de9e5e2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279900
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Deepak Nibade
2020-01-13 15:33:30 +05:30
committed by Alex Waterman
parent a0dede3a85
commit 6acd7924c5
2 changed files with 29 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.c
View File

@@ -777,6 +777,11 @@ fail:
return ret;
}
static u32 test_gr_get_min_gpm_fifo_depth(struct gk20a *g)
{
return 0;
}
int test_gr_init_hal_error_injection(struct unit_module *m,
struct gk20a *g, void *args)
{
@@ -785,6 +790,7 @@ int test_gr_init_hal_error_injection(struct unit_module *m,
struct nvgpu_gr_ctx_desc *desc;
struct nvgpu_gr_ctx *gr_ctx = NULL;
u32 size;
struct gpu_ops gops = g->ops;
g->ops.mm.cache.l2_flush = dummy_l2_flush;
@@ -836,6 +842,22 @@ int test_gr_init_hal_error_injection(struct unit_module *m,
EXPECT_BUG(g->ops.gr.init.get_attrib_cb_size(g, 0));
EXPECT_BUG(g->ops.gr.init.get_alpha_cb_size(g, 0));
/*
* Make g->ops.gr.init.get_min_gpm_fifo_depth return zero, so that
* we choose data as 0 in gp10b_gr_init_commit_global_bundle_cb()
* and program it.
* Ensure that 0 was programmed in corresponding field in
* register gr_pd_ab_dist_cfg2_r() by reading it back.
*/
g->ops.gr.init.get_min_gpm_fifo_depth = test_gr_get_min_gpm_fifo_depth;
g->ops.gr.init.commit_global_bundle_cb(g, gr_ctx, 0xffff, 0xffff, false);
if (nvgpu_readl(g, gr_pd_ab_dist_cfg2_r()) !=
g->ops.gr.init.get_bundle_cb_token_limit(g)) {
unit_return_fail(m, "expected value not set");
}
g->ops = gops;
/* cleanup */
nvgpu_gr_ctx_free_patch_ctx(g, vm, gr_ctx);
nvgpu_free_gr_ctx_struct(g, gr_ctx);

8
userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.h
View File

@@ -261,7 +261,9 @@ int test_gr_init_hal_config_error_injection(struct unit_module *m,
* gops_gr_init.get_attrib_cb_size,
* gv11b_gr_init_get_attrib_cb_size,
* gops_gr_init.get_alpha_cb_size,
* gv11b_gr_init_get_alpha_cb_size
* gv11b_gr_init_get_alpha_cb_size,
* gops_gr_init.commit_global_bundle_cb,
* gp10b_gr_init_commit_global_bundle_cb
*
* Input: gr_init_setup, gr_init_prepare, gr_init_support must have
* been executed successfully.
@@ -275,6 +277,10 @@ int test_gr_init_hal_config_error_injection(struct unit_module *m,
* - Call g->ops.gr.init.get_attrib_cb_size and g->ops.gr.init.get_alpha_cb_size
* with tpc_count = 0 for code coverage. Ensure that a BUG() is triggered.
* We are not interested in return value since tpc_count can never be 0.
* - Stub g->ops.gr.init.get_min_gpm_fifo_depth so that it returns 0. This will
* make g->ops.gr.init.commit_global_bundle_cb to write 0 in data field in
* register gr_pd_ab_dist_cfg2_r(). Verify same by reading back the register.
* - Restore all the gops operations.
* - Cleanup temporary resources.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL