gpu: nvgpu: ga10b: update l2 size using active sets

In some configurations, number of active l2 sets may be
reduced. Use active sets for reporting actual l2 size.
ga10b ltc.determine_L2_size_bytes hal is
updated to use active sets during l2 size calculation.

Bug 3279344

Change-Id: Icf1cf7ecd751e331a8ec3bd606f7eacb370e9027
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2595566
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2021-09-20 05:05:01 -07:00
committed by mobile promotions
parent 9266da636b
commit 6bc5e4bf3f
4 changed files with 50 additions and 1 deletions

View File

@@ -336,7 +336,7 @@ static const struct gops_ltc ga10b_ops_ltc = {
.ecc_init = gv11b_lts_ecc_init,
.init_ltc_support = nvgpu_init_ltc_support,
.ltc_remove_support = nvgpu_ltc_remove_support,
.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
.determine_L2_size_bytes = ga10b_determine_L2_size_bytes,
.init_fs_state = ga10b_ltc_init_fs_state,
.ltc_lts_set_mgmt_setup = ga10b_ltc_lts_set_mgmt_setup,
.flush = gm20b_flush_ltc,

View File

@@ -37,6 +37,7 @@ void ga10b_ltc_set_zbc_depth_entry(struct gk20a *g, u32 depth_val, u32 index);
void ga10b_ltc_init_fs_state(struct gk20a *g);
void ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g);
u64 ga10b_determine_L2_size_bytes(struct gk20a *g);
#ifdef CONFIG_NVGPU_DEBUGGER
u32 ga10b_ltc_pri_shared_addr(struct gk20a *g, u32 addr);

View File

@@ -23,6 +23,7 @@
#include <nvgpu/types.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/io.h>
#include <nvgpu/log.h>
#include <nvgpu/channel.h>
#include <nvgpu/regops.h>
#include <nvgpu/errata.h>
@@ -188,3 +189,46 @@ int ga10b_get_l2_max_ways_evict_last(struct gk20a *g, struct nvgpu_tsg *tsg,
return err;
}
u64 ga10b_determine_L2_size_bytes(struct gk20a *g)
{
u32 reg_val;
u32 slice_size;
u32 slices_per_l2;
u64 size = 0ULL;
#if defined(CONFIG_NVGPU_NON_FUSA)
u32 active_sets = 0U;
#endif
nvgpu_log_fn(g, " ");
reg_val = nvgpu_readl(g, ltc_ltc0_lts0_tstg_info_1_r());
slice_size = ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(reg_val);
slices_per_l2 = ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(reg_val);
/* L2 size = ltc_count * slice_size in KB * 1024 * slices_per_l2 */
size = nvgpu_safe_mult_u64(U64(nvgpu_ltc_get_ltc_count(g)),
nvgpu_safe_mult_u64(
nvgpu_safe_mult_u64(U64(slice_size), 1024ULL),
U64(slices_per_l2)));
#if defined(CONFIG_NVGPU_NON_FUSA)
reg_val = nvgpu_readl(g, ltc_ltcs_ltss_tstg_cfg1_r());
active_sets = ltc_ltcs_ltss_tstg_cfg1_active_sets_v(reg_val);
if (active_sets == ltc_ltcs_ltss_tstg_cfg1_active_sets_all_v()) {
nvgpu_log(g, gpu_dbg_info, "L2 active sets ALL");
} else if (active_sets ==
ltc_ltcs_ltss_tstg_cfg1_active_sets_half_v()) {
nvgpu_log(g, gpu_dbg_info, "L2 active sets HALF");
} else {
nvgpu_err(g, "Invalid L2 Active sets %d", active_sets);
return 0ULL;
}
/* Update size to reflect active sets */
size = size >> active_sets;
#endif
nvgpu_log(g, gpu_dbg_info, "L2 size: %llu\n", size);
nvgpu_log_fn(g, "done");
return size;
}

View File

@@ -67,6 +67,10 @@
((U32(v) & 0x1fU) << 16U)
#define ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_m() (U32(0x1fU) << 16U)
#define ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_v(r) (((r) >> 16U) & 0x1fU)
#define ltc_ltcs_ltss_tstg_cfg1_r() (0x0017e294U)
#define ltc_ltcs_ltss_tstg_cfg1_active_sets_v(r) (((r) >> 16U) & 0x3U)
#define ltc_ltcs_ltss_tstg_cfg1_active_sets_all_v() (0x00000000U)
#define ltc_ltcs_ltss_tstg_cfg1_active_sets_half_v() (0x00000001U)
#define ltc_ltcs_ltss_tstg_cfg2_r() (0x0017e298U)
#define ltc_ltcs_ltss_tstg_cfg2_vidmem_l1_promote_f(v) ((U32(v) & 0x3U) << 16U)
#define ltc_ltcs_ltss_tstg_cfg2_vidmem_l1_promote_m() (U32(0x3U) << 16U)