gpu: nvgpu: Create hal.mm.mm for misc MM HALs

There are many miscellaneous HALs for various MM related functionality.
This patch aims to migrate all the remaining MM code from the <chip>/
mm_<chip>.[ch] files in HAL files under hal/.

Much of this is fairly straightforward copy/paste and updates to the
HAL init files.

The exception to that is the move of the left over gv11b MMU fault
handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and
a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c
file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in
a subsequent patch.

JIRA NVGPU-2042

Change-Id: I12896de865d890a61afbcb71159cff486119ffb8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109050
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -148,6 +148,10 @@ nvgpu-y += \
 	common/nvlink/nvlink.o \
 	common/nvlink/nvlink_gv100.o \
 	common/nvlink/nvlink_tu104.o \
+	hal/mm/mm_gk20a.o \
+	hal/mm/mm_gm20b.o \
+	hal/mm/mm_gp10b.o \
+	hal/mm/mm_gv11b.o \
 	hal/mm/cache/flush_gk20a.o \
 	hal/mm/cache/flush_gv11b.o \
 	hal/mm/gmmu/gmmu_mmu_fault_gv11b.o \
@@ -542,8 +546,6 @@ nvgpu-y += \
 	common/ce/ce.o \
 	common/debugger.o \
 	gk20a/fifo_gk20a.o \
-	gk20a/mm_gk20a.o \
-	gm20b/mm_gm20b.o
 
 nvgpu-$(CONFIG_GK20A_VIDMEM) += \
 	common/mm/vidmem.o
@@ -588,7 +590,6 @@ nvgpu-$(CONFIG_GK20A_CYCLE_STATS) += \
 	common/cyclestats/cyclestats.o
 
 nvgpu-y += \
-	gp10b/mm_gp10b.o \
+	gv11b/mmu_fault_gv11b.o \
-	gv11b/mm_gv11b.o \
 	gv100/mm_gv100.o \
 	tu104/mm_tu104.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -243,12 +243,13 @@ srcs += common/sim/sim.c \
 	common/nvlink/nvlink.c \
 	common/fence/fence.c \
 	gk20a/fifo_gk20a.c \
-	gk20a/mm_gk20a.c \
+	gv11b/mmu_fault_gv11b.c \
-	gm20b/mm_gm20b.c \
-	gp10b/mm_gp10b.c \
-	gv11b/mm_gv11b.c \
 	gv100/mm_gv100.c \
 	tu104/mm_tu104.c \
+	hal/mm/mm_gk20a.c \
+	hal/mm/mm_gm20b.c \
+	hal/mm/mm_gp10b.c \
+	hal/mm/mm_gv11b.c \
 	hal/mm/cache/flush_gk20a.c \
 	hal/mm/cache/flush_gv11b.c \
 	hal/mm/gmmu/gmmu_mmu_fault_gv11b.c \

drivers/gpu/nvgpu/common/mm/allocators/nvgpu_allocator.c

@@ -25,7 +25,6 @@
 #include <nvgpu/allocator.h>
 #include <nvgpu/gk20a.h>
 
-#include "gk20a/mm_gk20a.h"
 
 u64 nvgpu_alloc_length(struct nvgpu_allocator *a)
 {

drivers/gpu/nvgpu/common/mm/gmmu/page_table.c

@@ -36,7 +36,6 @@
 #include <nvgpu/types.h>
 #include <nvgpu/gk20a.h>
 
-#include "gk20a/mm_gk20a.h"
 
 #define __gmmu_dbg(g, attrs, fmt, args...)				\
 	do {								\

drivers/gpu/nvgpu/common/mm/vidmem.c

@@ -32,7 +32,6 @@
 #include <nvgpu/nvgpu_sgt.h>
 #include <nvgpu/fence.h>
 
-#include "gk20a/mm_gk20a.h"
 
 /*
  * This is expected to be called from the shutdown path (or the error path in

drivers/gpu/nvgpu/common/mm/vm.c

@@ -39,7 +39,6 @@
 #include <nvgpu/vgpu/vm_vgpu.h>
 #include <nvgpu/cbc.h>
 
-#include "gk20a/mm_gk20a.h"
 
 struct nvgpu_ctag_buffer_info {
 	u64			size;

drivers/gpu/nvgpu/common/mm/vm_area.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,7 +25,6 @@
 #include <nvgpu/barrier.h>
 #include <nvgpu/gk20a.h>
 
-#include "gk20a/mm_gk20a.h"
 
 struct nvgpu_vm_area *nvgpu_vm_area_find(struct vm_gk20a *vm, u64 addr)
 {

drivers/gpu/nvgpu/common/semaphore/semaphore.c

@@ -33,7 +33,6 @@
 
 #include "semaphore_priv.h"
 
-#include "gk20a/mm_gk20a.h"
 
 /*
  * Allocate a semaphore from the passed pool.

drivers/gpu/nvgpu/common/sync/channel_sync.c

@@ -38,7 +38,6 @@
 #include <nvgpu/fence.h>
 
 #include "channel_sync_priv.h"
-#include "gk20a/mm_gk20a.h"
 
 struct nvgpu_channel_sync *nvgpu_channel_sync_create(struct channel_gk20a *c,
 	bool user_managed)

drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c

@@ -38,7 +38,6 @@
 #include <nvgpu/fence.h>
 
 #include "channel_sync_priv.h"
-#include "gk20a/mm_gk20a.h"
 
 struct nvgpu_channel_sync_semaphore {
 	struct nvgpu_channel_sync ops;

drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c

@@ -37,7 +37,6 @@
 #include <nvgpu/fence.h>
 
 #include "channel_sync_priv.h"
-#include "gk20a/mm_gk20a.h"
 
 struct nvgpu_channel_sync_syncpt {
 	struct nvgpu_channel_sync ops;

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -33,6 +33,10 @@
 
 #include "hal/bus/bus_gk20a.h"
 #include "hal/bus/bus_gm20b.h"
+#include "hal/mm/mm_gk20a.h"
+#include "hal/mm/mm_gm20b.h"
+#include "hal/mm/mm_gp10b.h"
+#include "hal/mm/gmmu/gmmu_gk20a.h"
 #include "hal/mm/gmmu/gmmu_gm20b.h"
 #include "hal/mm/gmmu/gmmu_gp10b.h"
 #include "hal/regops/regops_gp10b.h"
@@ -89,10 +93,6 @@
 #include "common/vgpu/init/init_vgpu.h"
 #include "vgpu_hal_gp10b.h"
 
-#include "gp10b/mm_gp10b.h"
-
-#include "gm20b/mm_gm20b.h"
-
 #include <nvgpu/hw/gp10b/hw_pram_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
 
@@ -571,9 +571,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.vm_bind_channel = vgpu_vm_bind_channel,
 		.setup_hw = NULL,
 		.is_bar1_supported = gm20b_mm_is_bar1_supported,
-		.init_inst_block = gk20a_init_inst_block,
+		.init_inst_block = gk20a_mm_init_inst_block,
-		.init_bar2_vm = gp10b_init_bar2_vm,
+		.init_bar2_vm = gp10b_mm_init_bar2_vm,
-		.remove_bar2_vm = gp10b_remove_bar2_vm,
+		.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
 		.bar1_map_userd = vgpu_mm_bar1_map_userd,
 		.vm_as_alloc_share = vgpu_vm_as_alloc_share,
 		.vm_as_free_share = vgpu_vm_as_free_share,

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -22,6 +22,10 @@
 
 #include "hal/bus/bus_gk20a.h"
 #include "hal/bus/bus_gm20b.h"
+#include "hal/mm/mm_gm20b.h"
+#include "hal/mm/mm_gp10b.h"
+#include "hal/mm/mm_gv11b.h"
+#include "hal/mm/gmmu/gmmu_gk20a.h"
 #include "hal/mm/gmmu/gmmu_gm20b.h"
 #include "hal/mm/gmmu/gmmu_gp10b.h"
 #include "hal/regops/regops_gv11b.h"
@@ -102,10 +106,6 @@
 #include "common/vgpu/ptimer/ptimer_vgpu.h"
 #include "vgpu_hal_gv11b.h"
 
-#include <gm20b/mm_gm20b.h>
-
-#include <gp10b/mm_gp10b.h>
-
 #include <gv11b/mm_gv11b.h>
 
 #include <nvgpu/debugger.h>
@@ -665,9 +665,9 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.vm_bind_channel = vgpu_vm_bind_channel,
 		.setup_hw = NULL,
 		.is_bar1_supported = gv11b_mm_is_bar1_supported,
-		.init_inst_block = gv11b_init_inst_block,
+		.init_inst_block = gv11b_mm_init_inst_block,
-		.init_bar2_vm = gp10b_init_bar2_vm,
+		.init_bar2_vm = gp10b_mm_init_bar2_vm,
-		.remove_bar2_vm = gp10b_remove_bar2_vm,
+		.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
 		.fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy,
 		.bar1_map_userd = vgpu_mm_bar1_map_userd,
 		.vm_as_alloc_share = vgpu_vm_as_alloc_share,

drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c

@@ -33,8 +33,6 @@
 #include <nvgpu/vgpu/vgpu.h>
 
 #include "mm_vgpu.h"
-#include "gk20a/mm_gk20a.h"
-#include "gm20b/mm_gm20b.h"
 #include "common/vgpu/ivc/comm_vgpu.h"
 
 static int vgpu_init_mm_setup_sw(struct gk20a *g)

drivers/gpu/nvgpu/gk20a/mm_gk20a.h

@@ -1,94 +0,0 @@
-/*
- * Copyright (c) 2011-2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef MM_GK20A_H
-#define MM_GK20A_H
-
-#include <nvgpu/nvgpu_mem.h>
-#include <nvgpu/allocator.h>
-#include <nvgpu/vm.h>
-#include <nvgpu/list.h>
-#include <nvgpu/rbtree.h>
-#include <nvgpu/kref.h>
-
-struct compbit_store_desc {
-	struct nvgpu_mem mem;
-
-	/* The value that is written to the hardware. This depends on
-	 * on the number of ltcs and is not an address. */
-	u64 base_hw;
-};
-
-struct gk20a_buffer_state {
-	struct nvgpu_list_node list;
-
-	/* The valid compbits and the fence must be changed atomically. */
-	struct nvgpu_mutex lock;
-
-	/* Offset of the surface within the dma-buf whose state is
-	 * described by this struct (one dma-buf can contain multiple
-	 * surfaces with different states). */
-	size_t offset;
-
-	/* A bitmask of valid sets of compbits (0 = uncompressed). */
-	u32 valid_compbits;
-
-	/* The ZBC color used on this buffer. */
-	u32 zbc_color;
-
-	/* This struct reflects the state of the buffer when this
-	 * fence signals. */
-	struct nvgpu_fence_type *fence;
-};
-
-static inline struct gk20a_buffer_state *
-gk20a_buffer_state_from_list(struct nvgpu_list_node *node)
-{
-	return (struct gk20a_buffer_state *)
-		((uintptr_t)node - offsetof(struct gk20a_buffer_state, list));
-};
-
-struct gk20a;
-struct channel_gk20a;
-
-#define dev_from_vm(vm) dev_from_gk20a(vm->mm->g)
-
-void gk20a_mm_ltc_isr(struct gk20a *g);
-
-bool gk20a_mm_mmu_debug_mode_enabled(struct gk20a *g);
-
-int gk20a_alloc_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block);
-void gk20a_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm,
-		u32 big_page_size);
-int gk20a_init_mm_setup_hw(struct gk20a *g);
-
-/* vm-as interface */
-struct nvgpu_as_alloc_space_args;
-struct nvgpu_as_free_space_args;
-int gk20a_vm_release_share(struct gk20a_as_share *as_share);
-
-void pde_range_from_vaddr_range(struct vm_gk20a *vm,
-					      u64 addr_lo, u64 addr_hi,
-					      u32 *pde_lo, u32 *pde_hi);
-u32 gk20a_mm_get_iommu_bit(struct gk20a *g);
-u64 gk20a_mm_bar1_map_userd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset);
-#endif /* MM_GK20A_H */

drivers/gpu/nvgpu/gv11b/mm_gv11b.h

@@ -1,6 +1,6 @@
 /*
  * GV11B MM
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,12 +25,7 @@
 #define MM_GV11B_H
 
 struct gk20a;
-struct nvgpu_mem;
-struct vm_gk20a;
 
-bool gv11b_mm_is_bar1_supported(struct gk20a *g);
-void gv11b_init_inst_block(struct nvgpu_mem *inst_block,
-		struct vm_gk20a *vm, u32 big_page_size);
 void gv11b_mm_fault_info_mem_destroy(struct gk20a *g);
 void gv11b_mm_mmu_fault_disable_hw(struct gk20a *g);
 

drivers/gpu/nvgpu/gv11b/mmu_fault_gv11b.c

@@ -29,39 +29,12 @@
 #include <nvgpu/enabled.h>
 #include <nvgpu/gk20a.h>
 
-#include "gk20a/mm_gk20a.h"
 
-#include "gp10b/mm_gp10b.h"
 
 #include "mm_gv11b.h"
 
 #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
 
-bool gv11b_mm_is_bar1_supported(struct gk20a *g)
-{
-	return false;
-}
-
-void gv11b_init_inst_block(struct nvgpu_mem *inst_block,
-		struct vm_gk20a *vm, u32 big_page_size)
-{
-	struct gk20a *g = gk20a_from_vm(vm);
-	u64 pdb_addr = nvgpu_pd_gpu_addr(g, &vm->pdb);
-
-	nvgpu_log_info(g, "inst block phys = 0x%llx, kv = 0x%p",
-		nvgpu_inst_block_addr(g, inst_block), inst_block->cpu_va);
-
-	g->ops.ramin.init_pdb(g, inst_block, pdb_addr, vm->pdb.mem);
-
-	if ((big_page_size != 0U) && (g->ops.ramin.set_big_page_size != NULL)) {
-		g->ops.ramin.set_big_page_size(g, inst_block, big_page_size);
-	}
-
-	if (g->ops.ramin.init_subctx_pdb != NULL) {
-		g->ops.ramin.init_subctx_pdb(g, inst_block, vm->pdb.mem, false);
-	}
-}
-
 void gv11b_mm_mmu_fault_disable_hw(struct gk20a *g)
 {
 	nvgpu_mutex_acquire(&g->mm.hub_isr_mutex);

drivers/gpu/nvgpu/hal/fb/fb_gv11b.c

@@ -38,7 +38,6 @@
 #include <nvgpu/nvgpu_err.h>
 #include <nvgpu/ltc.h>
 
-#include "gk20a/mm_gk20a.h"
 
 #include "fb_gm20b.h"
 #include "fb_gp10b.h"

drivers/gpu/nvgpu/hal/fb/fb_mmu_fault_gv11b.c

@@ -42,8 +42,6 @@
 #include "hal/fb/fb_mmu_fault_gv11b.h"
 #include "hal/mm/gmmu/gmmu_mmu_fault_gv11b.h"
 
-#include "gk20a/mm_gk20a.h"
-
 #include "fb_gm20b.h"
 #include "fb_gp10b.h"
 #include "fb_gv11b.h"

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -41,6 +41,8 @@
 #include <nvgpu/pmu/pmu_perfmon.h>
 #include <nvgpu/gr/fecs_trace.h>
 
+#include "hal/mm/mm_gk20a.h"
+#include "hal/mm/mm_gm20b.h"
 #include "hal/mm/cache/flush_gk20a.h"
 #include "hal/mm/gmmu/gmmu_gk20a.h"
 #include "hal/mm/gmmu/gmmu_gm20b.h"
@@ -100,8 +102,6 @@
 #include "common/fifo/channel_gm20b.h"
 #include "common/pmu/pg/pg_sw_gm20b.h"
 
-#include "gm20b/mm_gm20b.h"
-
 #include "hal_gm20b.h"
 
 #include <nvgpu/hw/gm20b/hw_proj_gm20b.h>
@@ -852,7 +852,7 @@ static const struct gpu_ops gm20b_ops = {
 		.vm_bind_channel = nvgpu_vm_bind_channel,
 		.setup_hw = nvgpu_mm_setup_hw,
 		.is_bar1_supported = gm20b_mm_is_bar1_supported,
-		.init_inst_block = gk20a_init_inst_block,
+		.init_inst_block = gk20a_mm_init_inst_block,
 		.bar1_map_userd = gk20a_mm_bar1_map_userd,
 		.cache = {
 			.fb_flush = gk20a_mm_fb_flush,

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -41,6 +41,9 @@
 #include <nvgpu/gr/gr_intr.h>
 #include <nvgpu/pmu/pmu_perfmon.h>
 
+#include "hal/mm/mm_gk20a.h"
+#include "hal/mm/mm_gm20b.h"
+#include "hal/mm/mm_gp10b.h"
 #include "hal/mm/cache/flush_gk20a.h"
 #include "hal/mm/gmmu/gmmu_gm20b.h"
 #include "hal/mm/gmmu/gmmu_gp10b.h"
@@ -121,9 +124,6 @@
 #include "common/fifo/channel_gm20b.h"
 #include "common/clk_arb/clk_arb_gp10b.h"
 
-#include "gp10b/mm_gp10b.h"
-#include "gm20b/mm_gm20b.h"
-
 #include "hal_gp10b.h"
 
 #include <nvgpu/hw/gp10b/hw_proj_gp10b.h>
@@ -929,9 +929,9 @@ static const struct gpu_ops gp10b_ops = {
 		.vm_bind_channel = nvgpu_vm_bind_channel,
 		.setup_hw = nvgpu_mm_setup_hw,
 		.is_bar1_supported = gm20b_mm_is_bar1_supported,
-		.init_inst_block = gk20a_init_inst_block,
+		.init_inst_block = gk20a_mm_init_inst_block,
-		.init_bar2_vm = gp10b_init_bar2_vm,
+		.init_bar2_vm = gp10b_mm_init_bar2_vm,
-		.remove_bar2_vm = gp10b_remove_bar2_vm,
+		.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
 		.bar1_map_userd = gk20a_mm_bar1_map_userd,
 		.cache = {
 			.fb_flush = gk20a_mm_fb_flush,

drivers/gpu/nvgpu/hal/init/hal_gv100.c

@@ -22,6 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#include "hal/mm/mm_gp10b.h"
+#include "hal/mm/mm_gv11b.h"
 #include "hal/mm/cache/flush_gk20a.h"
 #include "hal/mm/cache/flush_gv11b.h"
 #include "hal/mm/gmmu/gmmu_gm20b.h"
@@ -149,11 +151,6 @@
 #include "common/vbios/bios_sw_gp106.h"
 #include "common/vbios/bios_sw_gv100.h"
 
-
-#include "gm20b/mm_gm20b.h"
-
-#include "gp10b/mm_gp10b.h"
-
 #include "gv11b/mm_gv11b.h"
 
 #include "hal_gv100.h"
@@ -1125,9 +1122,9 @@ static const struct gpu_ops gv100_ops = {
 		.vm_bind_channel = nvgpu_vm_bind_channel,
 		.setup_hw = nvgpu_mm_setup_hw,
 		.is_bar1_supported = gv11b_mm_is_bar1_supported,
-		.init_inst_block = gv11b_init_inst_block,
+		.init_inst_block = gv11b_mm_init_inst_block,
-		.init_bar2_vm = gp10b_init_bar2_vm,
+		.init_bar2_vm = gp10b_mm_init_bar2_vm,
-		.remove_bar2_vm = gp10b_remove_bar2_vm,
+		.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
 		.fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy,
 		.mmu_fault_disable_hw = gv11b_mm_mmu_fault_disable_hw,
 		.get_flush_retries = gv100_mm_get_flush_retries,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -30,6 +30,8 @@
 #include <nvgpu/gr/gr.h>
 #include <nvgpu/pmu/pmu_perfmon.h>
 
+#include "hal/mm/mm_gp10b.h"
+#include "hal/mm/mm_gv11b.h"
 #include "hal/mm/cache/flush_gk20a.h"
 #include "hal/mm/cache/flush_gv11b.h"
 #include "hal/mm/gmmu/gmmu_gm20b.h"
@@ -140,9 +142,6 @@
 #include "common/fifo/channel_gv11b.h"
 #include "common/clk_arb/clk_arb_gp10b.h"
 
-#include "gm20b/mm_gm20b.h"
-#include "gp10b/mm_gp10b.h"
-
 #include "hal_gv11b.h"
 #include "gv11b/mm_gv11b.h"
 
@@ -1095,9 +1094,9 @@ static const struct gpu_ops gv11b_ops = {
 		.vm_bind_channel = nvgpu_vm_bind_channel,
 		.setup_hw = nvgpu_mm_setup_hw,
 		.is_bar1_supported = gv11b_mm_is_bar1_supported,
-		.init_inst_block = gv11b_init_inst_block,
+		.init_inst_block = gv11b_mm_init_inst_block,
-		.init_bar2_vm = gp10b_init_bar2_vm,
+		.init_bar2_vm = gp10b_mm_init_bar2_vm,
-		.remove_bar2_vm = gp10b_remove_bar2_vm,
+		.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
 		.fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy,
 		.mmu_fault_disable_hw = gv11b_mm_mmu_fault_disable_hw,
 		.bar1_map_userd = NULL,

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -22,6 +22,9 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#include "hal/mm/mm_gm20b.h"
+#include "hal/mm/mm_gp10b.h"
+#include "hal/mm/mm_gv11b.h"
 #include "hal/mm/cache/flush_gk20a.h"
 #include "hal/mm/cache/flush_gv11b.h"
 #include "hal/mm/gmmu/gmmu_gm20b.h"
@@ -165,15 +168,11 @@
 #include "common/fifo/channel_gv100.h"
 #include "common/clk_arb/clk_arb_gv100.h"
 
-#include "gm20b/mm_gm20b.h"
-
 #include "hal/clk/clk_gv100.h"
 
 #include "common/vbios/bios_sw_gp106.h"
 #include "common/vbios/bios_sw_tu104.h"
 
-#include "gp10b/mm_gp10b.h"
-
 #include "gv11b/mm_gv11b.h"
 
 #include "tu104/mm_tu104.h"
@@ -1162,9 +1161,9 @@ static const struct gpu_ops tu104_ops = {
 		.vm_bind_channel = nvgpu_vm_bind_channel,
 		.setup_hw = nvgpu_mm_setup_hw,
 		.is_bar1_supported = gv11b_mm_is_bar1_supported,
-		.init_inst_block = gv11b_init_inst_block,
+		.init_inst_block = gv11b_mm_init_inst_block,
-		.init_bar2_vm = gp10b_init_bar2_vm,
+		.init_bar2_vm = gp10b_mm_init_bar2_vm,
-		.remove_bar2_vm = gp10b_remove_bar2_vm,
+		.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
 		.fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy,
 		.mmu_fault_disable_hw = gv11b_mm_mmu_fault_disable_hw,
 		.get_flush_retries = tu104_mm_get_flush_retries,

drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c

@@ -265,3 +265,8 @@ const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g,
 	return (big_page_size == SZ_64K) ?
 		 gk20a_mm_levels_64k : gk20a_mm_levels_128k;
 }
+
+u32 gk20a_mm_get_iommu_bit(struct gk20a *g)
+{
+	return 34;
+}

drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.h

@@ -43,5 +43,6 @@ u32 gk20a_get_pde_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
 				struct nvgpu_gmmu_pd *pd, u32 pd_idx);
 u32 gk20a_get_pte_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
 				struct nvgpu_gmmu_pd *pd, u32 pd_idx);
+u32 gk20a_mm_get_iommu_bit(struct gk20a *g);
 
 #endif

drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_mmu_fault_gv11b.c

@@ -43,8 +43,6 @@
 #include <hal/fb/fb_mmu_fault_gv11b.h>
 #include <hal/mm/gmmu/gmmu_mmu_fault_gv11b.h>
 
-#include "gk20a/mm_gk20a.h"
-
 #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
 
 static int gv11b_fb_fix_page_fault(struct gk20a *g,

drivers/gpu/nvgpu/hal/mm/mm_gk20a.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -20,69 +20,13 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#include <trace/events/gk20a.h>
-
-#include <nvgpu/mm.h>
-#include <nvgpu/vm.h>
-#include <nvgpu/vm_area.h>
-#include <nvgpu/dma.h>
-#include <nvgpu/kmem.h>
-#include <nvgpu/timers.h>
-#include <nvgpu/pramin.h>
-#include <nvgpu/list.h>
-#include <nvgpu/nvgpu_mem.h>
-#include <nvgpu/allocator.h>
-#include <nvgpu/semaphore.h>
-#include <nvgpu/page_allocator.h>
-#include <nvgpu/log.h>
-#include <nvgpu/bug.h>
-#include <nvgpu/log2.h>
-#include <nvgpu/enabled.h>
-#include <nvgpu/vidmem.h>
-#include <nvgpu/sizes.h>
-#include <nvgpu/io.h>
-#include <nvgpu/utils.h>
 #include <nvgpu/gk20a.h>
-#include <nvgpu/channel.h>
+#include <nvgpu/gmmu.h>
-#include <nvgpu/pd_cache.h>
+#include <nvgpu/mm.h>
-#include <nvgpu/fence.h>
 
 #include "mm_gk20a.h"
 
-#include <nvgpu/hw/gk20a/hw_pram_gk20a.h>
+void gk20a_mm_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm,
-
-/*
- * GPU mapping life cycle
- * ======================
- *
- * Kernel mappings
- * ---------------
- *
- * Kernel mappings are created through vm.map(..., false):
- *
- *  - Mappings to the same allocations are reused and refcounted.
- *  - This path does not support deferred unmapping (i.e. kernel must wait for
- *    all hw operations on the buffer to complete before unmapping).
- *  - References to dmabuf are owned and managed by the (kernel) clients of
- *    the gk20a_vm layer.
- *
- *
- * User space mappings
- * -------------------
- *
- * User space mappings are created through as.map_buffer -> vm.map(..., true):
- *
- *  - Mappings to the same allocations are reused and refcounted.
- *  - This path supports deferred unmapping (i.e. we delay the actual unmapping
- *    until all hw operations have completed).
- *  - References to dmabuf are owned and managed by the vm_gk20a
- *    layer itself. vm.map acquires these refs, and sets
- *    mapped_buffer->own_mem_ref to record that we must release the refs when we
- *    actually unmap.
- *
- */
-
-void gk20a_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm,
 			      u32 big_page_size)
 {
 	struct gk20a *g = gk20a_from_vm(vm);
@@ -100,11 +44,6 @@ void gk20a_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm,
 	}
 }
 
-u32 gk20a_mm_get_iommu_bit(struct gk20a *g)
-{
-	return 34;
-}
-
 u64 gk20a_mm_bar1_map_userd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset)
 {
 	struct fifo_gk20a *f = &g->fifo;

drivers/gpu/nvgpu/hal/mm/mm_gk20a.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef HAL_MM_MM_GK20A_H
+#define HAL_MM_MM_GK20A_H
+
+#include <nvgpu/types.h>
+
+struct nvgpu_mem;
+struct vm_gk20a;
+
+void gk20a_mm_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm,
+			      u32 big_page_size);
+u64 gk20a_mm_bar1_map_userd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset);
+
+#endif

drivers/gpu/nvgpu/hal/mm/mm_gm20b.c

@@ -1,7 +1,5 @@
 /*
- * GM20B MMU
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,13 +20,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#include <nvgpu/sizes.h>
-#include <nvgpu/gk20a.h>
-
 #include "mm_gm20b.h"
 
-#include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h>
-
 bool gm20b_mm_is_bar1_supported(struct gk20a *g)
 {
 	return true;

drivers/gpu/nvgpu/hal/mm/mm_gm20b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -20,14 +20,13 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef NVGPU_GM20B_MM_GM20B_H
+#ifndef HAL_MM_MM_GM20B_H
-#define NVGPU_GM20B_MM_GM20B_H
+#define HAL_MM_MM_GM20B_H
+
+#include <nvgpu/types.h>
+
 struct gk20a;
 
-#define PDE_ADDR_START(x, y)	((x) &  ~((0x1UL << (y)) - 1))
-#define PDE_ADDR_END(x, y)	((x) | ((0x1UL << (y)) - 1))
-
-bool gm20b_mm_support_sparse(struct gk20a *g);
 bool gm20b_mm_is_bar1_supported(struct gk20a *g);
 
-#endif /* NVGPU_GM20B_MM_GM20B_H */
+#endif

drivers/gpu/nvgpu/hal/mm/mm_gp10b.c

@@ -1,7 +1,5 @@
 /*
- * GP10B MMU
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,19 +20,13 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#include <nvgpu/mm.h>
-#include <nvgpu/dma.h>
-#include <nvgpu/gmmu.h>
-#include <nvgpu/pd_cache.h>
-#include <nvgpu/sizes.h>
-#include <nvgpu/utils.h>
 #include <nvgpu/gk20a.h>
-#include <nvgpu/bug.h>
+#include <nvgpu/mm.h>
+#include <nvgpu/vm.h>
 
-#include "gm20b/mm_gm20b.h"
 #include "mm_gp10b.h"
 
-int gp10b_init_bar2_vm(struct gk20a *g)
+int gp10b_mm_init_bar2_vm(struct gk20a *g)
 {
 	int err;
 	struct mm_gk20a *mm = &g->mm;
@@ -68,7 +60,7 @@ clean_up_va:
 }
 
 
-void gp10b_remove_bar2_vm(struct gk20a *g)
+void gp10b_mm_remove_bar2_vm(struct gk20a *g)
 {
 	struct mm_gk20a *mm = &g->mm;
 

drivers/gpu/nvgpu/hal/mm/mm_gp10b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -20,15 +20,12 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef MM_GP10B_H
+#ifndef HAL_MM_MM_GP10B_H
-#define MM_GP10B_H
+#define HAL_MM_MM_GP10B_H
 
 struct gk20a;
-struct gk20a_mmu_level;
-struct nvgpu_mem;
-struct vm_gk20a;
 
-int gp10b_init_bar2_vm(struct gk20a *g);
+int gp10b_mm_init_bar2_vm(struct gk20a *g);
-void gp10b_remove_bar2_vm(struct gk20a *g);
+void gp10b_mm_remove_bar2_vm(struct gk20a *g);
 
 #endif

drivers/gpu/nvgpu/hal/mm/mm_gv11b.c

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/gmmu.h>
+#include <nvgpu/mm.h>
+
+#include "mm_gv11b.h"
+
+void gv11b_mm_init_inst_block(struct nvgpu_mem *inst_block,
+			      struct vm_gk20a *vm, u32 big_page_size)
+{
+	struct gk20a *g = gk20a_from_vm(vm);
+	u64 pdb_addr = nvgpu_pd_gpu_addr(g, &vm->pdb);
+
+	nvgpu_log_info(g, "inst block phys = 0x%llx, kv = 0x%p",
+		nvgpu_inst_block_addr(g, inst_block), inst_block->cpu_va);
+
+	g->ops.ramin.init_pdb(g, inst_block, pdb_addr, vm->pdb.mem);
+
+	if ((big_page_size != 0U) && (g->ops.ramin.set_big_page_size != NULL)) {
+		g->ops.ramin.set_big_page_size(g, inst_block, big_page_size);
+	}
+
+	if (g->ops.ramin.init_subctx_pdb != NULL) {
+		g->ops.ramin.init_subctx_pdb(g, inst_block, vm->pdb.mem, false);
+	}
+}
+
+bool gv11b_mm_is_bar1_supported(struct gk20a *g)
+{
+	return false;
+}

drivers/gpu/nvgpu/hal/mm/mm_gv11b.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef HAL_MM_MM_GV11B_H
+#define HAL_MM_MM_GV11B_H
+
+#include <nvgpu/types.h>
+
+struct nvgpu_mem;
+struct vm_gk20a;
+
+void gv11b_mm_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm,
+			      u32 big_page_size);
+bool gv11b_mm_is_bar1_supported(struct gk20a *g);
+
+#endif

drivers/gpu/nvgpu/include/nvgpu/as.h

@@ -1,7 +1,7 @@
 /*
  * GK20A Address Spaces
  *
- * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -46,6 +46,7 @@ struct gk20a_as_share {
 #define NVGPU_AS_ALLOC_UNIFIED_VA		BIT32(1)
 
 int gk20a_as_release_share(struct gk20a_as_share *as_share);
+int gk20a_vm_release_share(struct gk20a_as_share *as_share);
 
 /* if big_page_size == 0, the default big page size is used */
 int gk20a_as_alloc_share(struct gk20a *g, u32 big_page_size,

drivers/gpu/nvgpu/include/nvgpu/cbc.h

@@ -25,8 +25,7 @@
 
 #include <nvgpu/types.h>
 #include <nvgpu/comptags.h>
-
+#include <nvgpu/nvgpu_mem.h>
-#include "gk20a/mm_gk20a.h"
 
 struct gk20a;
 
@@ -36,6 +35,15 @@ enum nvgpu_cbc_op {
 	nvgpu_cbc_op_invalidate,
 };
 
+struct compbit_store_desc {
+	struct nvgpu_mem mem;
+
+	/*
+	 * The value that is written to the hardware. This depends on
+	 * on the number of ltcs and is not an address.
+	 */
+	u64 base_hw;
+};
 
 struct nvgpu_cbc {
 	u32 compbit_backing_size;

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -87,6 +87,7 @@ struct nvgpu_fecs_host_intr_status;
 struct nvgpu_fecs_ecc_status;
 struct _resmgr_context;
 struct nvgpu_gpfifo_entry;
+struct vm_gk20a_mapping_batch;
 
 enum nvgpu_unit;
 enum nvgpu_flush_op;

drivers/gpu/nvgpu/include/nvgpu/mm.h

@@ -23,6 +23,7 @@
 #ifndef NVGPU_MM_H
 #define NVGPU_MM_H
 
+#include <nvgpu/vm.h>
 #include <nvgpu/types.h>
 #include <nvgpu/cond.h>
 #include <nvgpu/thread.h>

drivers/gpu/nvgpu/libnvgpu-drv.export

@@ -35,12 +35,10 @@ gm20b_fb_tlb_invalidate
 gm20b_fuse_status_opt_gpc
 gm20b_ramin_set_big_page_size
 gp10b_fb_compression_page_size
-gp10b_init_bar2_vm
 gp10b_mm_get_default_big_page_size
 gp10b_mm_get_iommu_bit
 gp10b_mm_get_mmu_levels
 gp10b_ramin_init_pdb
-gp10b_remove_bar2_vm
 gv11b_channel_count
 gv11b_fb_intr_enable
 gv11b_fb_fault_buf_configure_hw
@@ -49,9 +47,9 @@ gv11b_fb_init_hw
 gv11b_fb_is_fault_buf_enabled
 gv11b_fb_intr_is_mmu_fault_pending
 gv11b_gpu_phys_addr
-gv11b_init_inst_block
 gv11b_mm_fault_info_mem_destroy
 gv11b_mm_is_bar1_supported
+gv11b_mm_init_inst_block
 gv11b_mm_l2_flush
 gv11b_mm_mmu_fault_disable_hw
 gv11b_mc_is_mmu_fault_pending

drivers/gpu/nvgpu/os/linux/cde.c

@@ -43,8 +43,6 @@
 
 #include <nvgpu/linux/vm.h>
 
-#include "gk20a/mm_gk20a.h"
-
 #include "cde.h"
 #include "os_linux.h"
 #include "dmabuf.h"

drivers/gpu/nvgpu/os/linux/dmabuf.h

@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+* Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -28,7 +28,35 @@ struct dma_buf_attachment;
 struct device;
 
 struct gk20a;
-struct gk20a_buffer_state;
+
+struct gk20a_buffer_state {
+	struct nvgpu_list_node list;
+
+	/* The valid compbits and the fence must be changed atomically. */
+	struct nvgpu_mutex lock;
+
+	/* Offset of the surface within the dma-buf whose state is
+	 * described by this struct (one dma-buf can contain multiple
+	 * surfaces with different states). */
+	size_t offset;
+
+	/* A bitmask of valid sets of compbits (0 = uncompressed). */
+	u32 valid_compbits;
+
+	/* The ZBC color used on this buffer. */
+	u32 zbc_color;
+
+	/* This struct reflects the state of the buffer when this
+	 * fence signals. */
+	struct nvgpu_fence_type *fence;
+};
+
+static inline struct gk20a_buffer_state *
+gk20a_buffer_state_from_list(struct nvgpu_list_node *node)
+{
+	return (struct gk20a_buffer_state *)
+		((uintptr_t)node - offsetof(struct gk20a_buffer_state, list));
+};
 
 struct gk20a_dmabuf_priv {
 	struct nvgpu_mutex lock;

drivers/gpu/nvgpu/os/linux/dmabuf_vidmem.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -32,7 +32,6 @@
 #include <nvgpu/linux/vm.h>
 #include <nvgpu/linux/dma.h>
 
-#include "gk20a/mm_gk20a.h"
 #include "dmabuf_vidmem.h"
 
 bool nvgpu_addr_is_vidmem_page_alloc(u64 addr)

drivers/gpu/nvgpu/os/linux/nvgpu_mem.c

@@ -35,7 +35,6 @@
 #include "os_linux.h"
 #include "dmabuf_vidmem.h"
 
-#include "gk20a/mm_gk20a.h"
 #include "platform_gk20a.h"
 
 static u64 __nvgpu_sgl_ipa(struct gk20a *g, struct nvgpu_sgl *sgl)

drivers/gpu/nvgpu/os/linux/os_fence_android_sema.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -25,8 +25,6 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/channel_sync.h>
 
-#include "gk20a/mm_gk20a.h"
-
 #include "sync_sema_android.h"
 
 #include "../drivers/staging/android/sync.h"
@@ -101,4 +99,3 @@ int nvgpu_os_fence_sema_fdget(struct nvgpu_os_fence *fence_out,
 
 	return 0;
 }
-

drivers/gpu/nvgpu/os/linux/os_fence_android_syncpt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -27,8 +27,6 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/channel_sync.h>
 
-#include "gk20a/mm_gk20a.h"
-
 #include "../drivers/staging/android/sync.h"
 
 static const struct nvgpu_os_fence_ops syncpt_ops = {

drivers/gpu/nvgpu/os/linux/vm.c

@@ -31,13 +31,14 @@
 #include <nvgpu/linux/vm.h>
 #include <nvgpu/linux/nvgpu_mem.h>
 
-#include "gk20a/mm_gk20a.h"
 
 #include "platform_gk20a.h"
 #include "os_linux.h"
 #include "dmabuf.h"
 #include "dmabuf_vidmem.h"
 
+#define dev_from_vm(vm) dev_from_gk20a(vm->mm->g)
+
 static u32 nvgpu_vm_translate_linux_flags(struct gk20a *g, u32 flags)
 {
 	u32 core_flags = 0;

userspace/Makefile.sources

@@ -28,8 +28,6 @@ HEADERS :=	\
 	$(NVGPU_SRC)/include/nvgpu/*.h		\
 	$(NVGPU_SRC)/include/nvgpu/hw/*/*.h	\
 	$(NVGPU_SRC)/gk20a/*.h			\
-	$(NVGPU_SRC)/gm20b/*.h			\
-	$(NVGPU_SRC)/gp10b/*.h			\
 	$(NVGPU_SRC)/gv11b/*.h			\
 	$(NVGPU_SRC)/tu104/*.h
 

userspace/units/mm/gmmu/page_table/page_table.c

@@ -37,6 +37,7 @@
 
 #include <gv11b/mm_gv11b.h>
 
+#include <hal/mm/mm_gv11b.h>
 #include <hal/mm/cache/flush_gk20a.h>
 #include <hal/mm/cache/flush_gv11b.h>
 #include <hal/mm/gmmu/gmmu_gp10b.h>
@@ -299,7 +300,7 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
 	g->ops.mm.gmmu.get_default_big_page_size =
 		gp10b_mm_get_default_big_page_size;
 	g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels;
-	g->ops.mm.init_inst_block = gv11b_init_inst_block;
+	g->ops.mm.init_inst_block = gv11b_mm_init_inst_block;
 	g->ops.mm.gmmu.map = nvgpu_gmmu_map_locked;
 	g->ops.mm.gmmu.unmap = nvgpu_gmmu_unmap_locked;
 	g->ops.mm.gmmu.gpu_phys_addr = gv11b_gpu_phys_addr;

userspace/units/mm/page_table_faults/page_table_faults.c

@@ -38,6 +38,7 @@
 #include "gv11b/mm_gv11b.h"
 #include "common/fifo/channel_gv11b.h"
 
+#include "hal/mm/mm_gv11b.h"
 #include "hal/mm/cache/flush_gk20a.h"
 #include "hal/mm/cache/flush_gv11b.h"
 #include "hal/mm/gmmu/gmmu_gp10b.h"
@@ -121,7 +122,7 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
 	g->ops.mm.gmmu.get_default_big_page_size =
 		gp10b_mm_get_default_big_page_size;
 	g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels;
-	g->ops.mm.init_inst_block = gv11b_init_inst_block;
+	g->ops.mm.init_inst_block = gv11b_mm_init_inst_block;
 	g->ops.mm.gmmu.map = nvgpu_gmmu_map_locked;
 	g->ops.mm.gmmu.unmap = nvgpu_gmmu_unmap_locked;
 	g->ops.mm.gmmu.gpu_phys_addr = gv11b_gpu_phys_addr;

userspace/units/mm/vm/vm.c

@@ -32,7 +32,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/nvgpu_sgt.h>
 #include <nvgpu/vm_area.h>
-#include <gp10b/mm_gp10b.h>
+
 #include <hal/mm/cache/flush_gk20a.h>
 #include <hal/mm/cache/flush_gv11b.h>
 #include <hal/mm/gmmu/gmmu_gp10b.h>