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gpu: nvgpu: add placeholder for IPA to PA

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Add __nvgpu_sgl_phys function that can be used to implement IPA
to PA translation in a subsequent change.
Adapt existing function prototypes to add pointer to gpu context,
as we will need to check if IPA to PA translation is needed.

JIRA EVLR-2442
Bug 200392719

Change-Id: I5a734c958c8277d1bf673c020dafb31263f142d6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1673142
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2018-03-07 09:23:53 -08:00
committed by mobile promotions
parent f94c9d19c1
commit 6c33a010d8
9 changed files with 37 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/gpu/nvgpu/common/linux/nvgpu_mem.c
View File

@@ -34,6 +34,11 @@
#include "gk20a/gk20a.h"
#include "gk20a/mm_gk20a.h"
static inline u64 __nvgpu_sgl_phys(struct gk20a *g, struct nvgpu_sgl *sgl)
{
return sg_phys((struct scatterlist *)sgl);
}
int nvgpu_mem_begin(struct gk20a *g, struct nvgpu_mem *mem)
{
void *cpu_va;
@@ -309,10 +314,12 @@ u64 nvgpu_mem_get_addr_sgl(struct gk20a *g, struct scatterlist *sgl)
{
if (nvgpu_is_enabled(g, NVGPU_MM_USE_PHYSICAL_SG) ||
!nvgpu_iommuable(g))
return g->ops.mm.gpu_phys_addr(g, NULL, sg_phys(sgl));
return g->ops.mm.gpu_phys_addr(g, NULL,
__nvgpu_sgl_phys(g, (struct nvgpu_sgl *)sgl));
if (sg_dma_address(sgl) == 0)
return g->ops.mm.gpu_phys_addr(g, NULL, sg_phys(sgl));
return g->ops.mm.gpu_phys_addr(g, NULL,
__nvgpu_sgl_phys(g, (struct nvgpu_sgl *)sgl));
if (sg_dma_address(sgl) == DMA_ERROR_CODE)
return 0;
@@ -376,7 +383,7 @@ u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem)
if (mem->aperture == APERTURE_VIDMEM)
return nvgpu_mem_get_addr(g, mem);
return sg_phys(mem->priv.sgt->sgl);
return __nvgpu_sgl_phys(g, (struct nvgpu_sgl *)mem->priv.sgt->sgl);
}
/*
@@ -501,9 +508,9 @@ static struct nvgpu_sgl *nvgpu_mem_linux_sgl_next(struct nvgpu_sgl *sgl)
return (struct nvgpu_sgl *)sg_next((struct scatterlist *)sgl);
}
static u64 nvgpu_mem_linux_sgl_phys(struct nvgpu_sgl *sgl)
static u64 nvgpu_mem_linux_sgl_phys(struct gk20a *g, struct nvgpu_sgl *sgl)
{
return (u64)sg_phys((struct scatterlist *)sgl);
return (u64)__nvgpu_sgl_phys(g, sgl);
}
static u64 nvgpu_mem_linux_sgl_dma(struct nvgpu_sgl *sgl)
@@ -522,7 +529,7 @@ static u64 nvgpu_mem_linux_sgl_gpu_addr(struct gk20a *g,
{
if (sg_dma_address((struct scatterlist *)sgl) == 0)
return g->ops.mm.gpu_phys_addr(g, attrs,
sg_phys((struct scatterlist *)sgl));
__nvgpu_sgl_phys(g, sgl));
if (sg_dma_address((struct scatterlist *)sgl) == DMA_ERROR_CODE)
return 0;

4
drivers/gpu/nvgpu/common/mm/gmmu.c
View File

@@ -543,7 +543,7 @@ static int __nvgpu_gmmu_do_update_page_table(struct vm_gk20a *vm,
}
phys_addr = g->ops.mm.gpu_phys_addr(g, attrs,
nvgpu_sgt_get_phys(sgt, sgl)) + space_to_skip;
nvgpu_sgt_get_phys(g, sgt, sgl)) + space_to_skip;
chunk_length = min(length,
nvgpu_sgt_get_length(sgt, sgl) - space_to_skip);
@@ -629,7 +629,7 @@ static int __nvgpu_gmmu_update_page_table(struct vm_gk20a *vm,
sgt ? "MAP" : "UNMAP",
virt_addr,
length,
sgt ? nvgpu_sgt_get_phys(sgt, sgt->sgl) : 0,
sgt ? nvgpu_sgt_get_phys(g, sgt, sgt->sgl) : 0,
space_to_skip,
page_size >> 10,
nvgpu_gmmu_perm_str(attrs->rw_flag),

7
drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
View File

@@ -81,9 +81,10 @@ struct nvgpu_sgl *nvgpu_sgt_get_next(struct nvgpu_sgt *sgt,
return sgt->ops->sgl_next(sgl);
}
u64 nvgpu_sgt_get_phys(struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl)
u64 nvgpu_sgt_get_phys(struct gk20a *g, struct nvgpu_sgt *sgt,
struct nvgpu_sgl *sgl)
{
return sgt->ops->sgl_phys(sgl);
return sgt->ops->sgl_phys(g, sgl);
}
u64 nvgpu_sgt_get_dma(struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl)
@@ -156,7 +157,7 @@ u64 nvgpu_sgt_alignment(struct gk20a *g, struct nvgpu_sgt *sgt)
* of the SGT.
*/
nvgpu_sgt_for_each_sgl(sgl, sgt) {
chunk_align = 1ULL << __ffs(nvgpu_sgt_get_phys(sgt, sgl) |
chunk_align = 1ULL << __ffs(nvgpu_sgt_get_phys(g, sgt, sgl) |
nvgpu_sgt_get_length(sgt, sgl));
if (align)

11
drivers/gpu/nvgpu/common/mm/page_allocator.c
View File

@@ -160,7 +160,7 @@ static struct nvgpu_sgl *nvgpu_page_alloc_sgl_next(struct nvgpu_sgl *sgl)
return (struct nvgpu_sgl *)sgl_impl->next;
}
static u64 nvgpu_page_alloc_sgl_phys(struct nvgpu_sgl *sgl)
static u64 nvgpu_page_alloc_sgl_phys(struct gk20a *g, struct nvgpu_sgl *sgl)
{
struct nvgpu_mem_sgl *sgl_impl = (struct nvgpu_mem_sgl *)sgl;
@@ -231,11 +231,12 @@ static void __nvgpu_free_pages(struct nvgpu_page_allocator *a,
bool free_buddy_alloc)
{
struct nvgpu_sgl *sgl = alloc->sgt.sgl;
struct gk20a *g = a->owner->g;
if (free_buddy_alloc) {
while (sgl) {
nvgpu_free(&a->source_allocator,
nvgpu_sgt_get_phys(&alloc->sgt, sgl));
nvgpu_sgt_get_phys(g, &alloc->sgt, sgl));
sgl = nvgpu_sgt_get_next(&alloc->sgt, sgl);
}
}
@@ -615,6 +616,7 @@ fail:
static struct nvgpu_page_alloc *__nvgpu_alloc_pages(
struct nvgpu_page_allocator *a, u64 len)
{
struct gk20a *g = a->owner->g;
struct nvgpu_page_alloc *alloc = NULL;
struct nvgpu_sgl *sgl;
u64 pages;
@@ -635,7 +637,7 @@ static struct nvgpu_page_alloc *__nvgpu_alloc_pages(
while (sgl) {
palloc_dbg(a, " Chunk %2d: 0x%010llx + 0x%llx",
i++,
nvgpu_sgt_get_phys(&alloc->sgt, sgl),
nvgpu_sgt_get_phys(g, &alloc->sgt, sgl),
nvgpu_sgt_get_length(&alloc->sgt, sgl));
sgl = nvgpu_sgt_get_next(&alloc->sgt, sgl);
}
@@ -779,6 +781,7 @@ static u64 nvgpu_page_alloc_fixed(struct nvgpu_allocator *__a,
struct nvgpu_page_allocator *a = page_allocator(__a);
struct nvgpu_page_alloc *alloc = NULL;
struct nvgpu_sgl *sgl;
struct gk20a *g = a->owner->g;
u64 aligned_len, pages;
int i = 0;
@@ -802,7 +805,7 @@ static u64 nvgpu_page_alloc_fixed(struct nvgpu_allocator *__a,
while (sgl) {
palloc_dbg(a, " Chunk %2d: 0x%010llx + 0x%llx",
i++,
nvgpu_sgt_get_phys(&alloc->sgt, sgl),
nvgpu_sgt_get_phys(g, &alloc->sgt, sgl),
nvgpu_sgt_get_length(&alloc->sgt, sgl));
sgl = nvgpu_sgt_get_next(&alloc->sgt, sgl);
}

4
drivers/gpu/nvgpu/common/mm/vidmem.c
View File

@@ -430,7 +430,7 @@ int nvgpu_vidmem_clear(struct gk20a *g, struct nvgpu_mem *mem)
err = gk20a_ce_execute_ops(g,
g->mm.vidmem.ce_ctx_id,
0,
nvgpu_sgt_get_phys(&alloc->sgt, sgl),
nvgpu_sgt_get_phys(g, &alloc->sgt, sgl),
nvgpu_sgt_get_length(&alloc->sgt, sgl),
0x00000000,
NVGPU_CE_DST_LOCATION_LOCAL_FB,
@@ -445,7 +445,7 @@ int nvgpu_vidmem_clear(struct gk20a *g, struct nvgpu_mem *mem)
}
vidmem_dbg(g, " > [0x%llx +0x%llx]",
nvgpu_sgt_get_phys(&alloc->sgt, sgl),
nvgpu_sgt_get_phys(g, &alloc->sgt, sgl),
nvgpu_sgt_get_length(&alloc->sgt, sgl));
gk20a_last_fence = gk20a_fence_out;

5
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -867,6 +867,7 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g)
struct fifo_gk20a *f = &g->fifo;
unsigned int chid, i;
int err = 0;
u64 userd_base;
gk20a_dbg_fn("");
@@ -929,9 +930,9 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g)
}
gk20a_dbg(gpu_dbg_map, "userd gpu va = 0x%llx", f->userd.gpu_va);
userd_base = nvgpu_mem_get_addr(g, &f->userd);
for (chid = 0; chid < f->num_channels; chid++) {
f->channel[chid].userd_iova =
nvgpu_mem_get_addr(g, &f->userd) +
f->channel[chid].userd_iova = userd_base +
chid * f->userd_entry_size;
f->channel[chid].userd_gpu_va =
f->userd.gpu_va + chid * f->userd_entry_size;

4
drivers/gpu/nvgpu/gk20a/pramin_gk20a.c
View File

@@ -34,7 +34,7 @@
u32 gk20a_pramin_enter(struct gk20a *g, struct nvgpu_mem *mem,
struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, u32 w)
{
u64 bufbase = nvgpu_sgt_get_phys(sgt, sgl);
u64 bufbase = nvgpu_sgt_get_phys(g, sgt, sgl);
u64 addr = bufbase + w * sizeof(u32);
u32 hi = (u32)((addr & ~(u64)0xfffff)
>> bus_bar0_window_target_bar0_window_base_shift_v());
@@ -48,7 +48,7 @@ u32 gk20a_pramin_enter(struct gk20a *g, struct nvgpu_mem *mem,
gk20a_dbg(gpu_dbg_mem,
"0x%08x:%08x begin for %p,%p at [%llx,%llx] (sz %llx)",
hi, lo, mem, sgl, bufbase,
bufbase + nvgpu_sgt_get_phys(sgt, sgl),
bufbase + nvgpu_sgt_get_phys(g, sgt, sgl),
nvgpu_sgt_get_length(sgt, sgl));
WARN_ON(!bufbase);

5
drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
View File

@@ -68,7 +68,7 @@ struct nvgpu_sgl;
struct nvgpu_sgt_ops {
struct nvgpu_sgl *(*sgl_next)(struct nvgpu_sgl *sgl);
u64 (*sgl_phys)(struct nvgpu_sgl *sgl);
u64 (*sgl_phys)(struct gk20a *g, struct nvgpu_sgl *sgl);
u64 (*sgl_dma)(struct nvgpu_sgl *sgl);
u64 (*sgl_length)(struct nvgpu_sgl *sgl);
u64 (*sgl_gpu_addr)(struct gk20a *g, struct nvgpu_sgl *sgl,
@@ -254,7 +254,8 @@ struct nvgpu_sgt *nvgpu_sgt_create_from_mem(struct gk20a *g,
struct nvgpu_sgl *nvgpu_sgt_get_next(struct nvgpu_sgt *sgt,
struct nvgpu_sgl *sgl);
u64 nvgpu_sgt_get_phys(struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl);
u64 nvgpu_sgt_get_phys(struct gk20a *g, struct nvgpu_sgt *sgt,
struct nvgpu_sgl *sgl);
u64 nvgpu_sgt_get_dma(struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl);
u64 nvgpu_sgt_get_length(struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl);
u64 nvgpu_sgt_get_gpu_addr(struct gk20a *g, struct nvgpu_sgt *sgt,

2
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c
View File

@@ -122,7 +122,7 @@ u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
continue;
}
phys_addr = nvgpu_sgt_get_phys(sgt, sgl) + space_to_skip;
phys_addr = nvgpu_sgt_get_phys(g, sgt, sgl) + space_to_skip;
chunk_length = min(size,
nvgpu_sgt_get_length(sgt, sgl) - space_to_skip);