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gpu: nvgpu: Export func definions for future usage

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Export below functions through the corresponding headers for the
consumption of other GPU enabling codes.
	gv11b_fb_copy_from_hw_fault_buf
	gv11b_mm_mmu_fault_handle_mmu_fault_refch
	gsp_get_emem_boundaries

Change-Id: If041d1983a6981f510d8dd622c95b1e80fa50e16
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2794239
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: V M S Seeta Rama Raju Mudundi <srajum@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Ramalingam C
2022-10-18 15:25:02 +00:00
committed by mobile promotions
parent 7ab770ae93
commit 6c9ae09d93
4 changed files with 13 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c
View File

@@ -292,7 +292,7 @@ void ga10b_gsp_enable_irq(struct gk20a *g, bool enable)
}
}
static int gsp_get_emem_boundaries(struct gk20a *g,
s32 ga10b_gsp_get_emem_boundaries(struct gk20a *g,
u32 *start_emem, u32 *end_emem)
{
u32 tag_width_shift = 0;
@@ -357,7 +357,7 @@ static int gsp_memcpy_params_check(struct gk20a *g, u32 dmem_addr,
goto exit;
}
status = gsp_get_emem_boundaries(g, &start_emem, &end_emem);
status = ga10b_gsp_get_emem_boundaries(g, &start_emem, &end_emem);
if (status != 0) {
goto exit;
}
@@ -402,7 +402,7 @@ static int ga10b_gsp_emem_transfer(struct gk20a *g, u32 dmem_addr, u8 *buf,
emem_d_offset = pgsp_ememd_r(port);
/* Only start address needed */
status = gsp_get_emem_boundaries(g, &start_emem, NULL);
status = ga10b_gsp_get_emem_boundaries(g, &start_emem, NULL);
if (status != 0) {
goto exit;
}

2
drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h
View File

@@ -48,6 +48,8 @@ int ga10b_gsp_flcn_copy_from_emem(struct gk20a *g,
/* interrupt */
void ga10b_gsp_enable_irq(struct gk20a *g, bool enable);
s32 ga10b_gsp_get_emem_boundaries(struct gk20a *g,
u32 *start_emem, u32 *end_emem);
void ga10b_gsp_isr(struct gk20a *g, struct nvgpu_gsp *gsp);
void ga10b_gsp_set_msg_intr(struct gk20a *g);
#endif /* CONFIG_NVGPU_GSP_SCHEDULER */

7
drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,5 +40,10 @@ void gv11b_mm_mmu_fault_handle_other_fault_notify(struct gk20a *g,
u32 fault_status);
void gv11b_mm_mmu_fault_parse_mmu_fault_info(struct mmu_fault_info *mmufault);
void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g,
struct nvgpu_mem *mem, u32 offset, struct mmu_fault_info *mmufault);
bool gv11b_mm_mmu_fault_handle_mmu_fault_refch(struct gk20a *g,
struct mmu_fault_info *mmufault, u32 *id_ptr,
unsigned int *id_type_ptr, unsigned int *rc_type_ptr);
#endif

4
drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c
View File

@@ -198,7 +198,7 @@ void gv11b_mm_mmu_fault_parse_mmu_fault_info(struct mmu_fault_info *mmufault)
*|V|R|P| gpc_id |0 0 0|t|0|acctp|0| client |RF0 0|faulttype|
*/
static void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g,
void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g,
struct nvgpu_mem *mem, u32 offset, struct mmu_fault_info *mmufault)
{
u32 rd32_val;
@@ -341,7 +341,7 @@ static bool gv11b_mm_mmu_fault_handle_mmu_fault_ce(struct gk20a *g,
return false;
}
static bool gv11b_mm_mmu_fault_handle_mmu_fault_refch(struct gk20a *g,
bool gv11b_mm_mmu_fault_handle_mmu_fault_refch(struct gk20a *g,
struct mmu_fault_info *mmufault, u32 *id_ptr,
unsigned int *id_type_ptr, unsigned int *rc_type_ptr)
{