nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-25 11:04:51 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Add CDE bits in FECS header

Browse Source 
In case of CDE channel, T1 (Tex) unit needs to be promoted to 128B
aligned, otherwise causes a HW deadlock. Gpu driver makes changes in
FECS header which FECS uses to configure the T1 promotions to aligned
128B accesses.

Bug 200096226

Change-Id: Ic006b2c7035bbeabe1081aeed968a6c6d11f9995
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/802327
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
sujeet baranwal
2015-09-22 08:56:13 -07:00
committed by Terje Bergstrom
parent 977acd877b
commit 6ceef08d52
4 changed files with 26 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/gk20a/cde_gk20a.c
View File

@@ -487,6 +487,9 @@ static int gk20a_init_cde_required_class(struct gk20a_cde_ctx *cde_ctx,
alloc_obj_ctx.class_num = required_class;
alloc_obj_ctx.flags = 0;
/* CDE enabled */
cde_ctx->ch->cde = true;
err = gk20a_alloc_obj_ctx(cde_ctx->ch, &alloc_obj_ctx);
if (err) {
gk20a_warn(&cde_ctx->pdev->dev, "cde: failed to allocate ctx. err=%d",

1
drivers/gpu/nvgpu/gk20a/channel_gk20a.h
View File

@@ -91,6 +91,7 @@ struct channel_gk20a {
bool bound;
bool first_init;
bool vpr;
bool cde;
pid_t pid;
struct mutex ioctl_lock;

11
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -1612,7 +1612,7 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
u32 virt_addr_lo;
u32 virt_addr_hi;
u32 i, v, data;
u32 i, v, data, cde_v;
int ret = 0;
void *ctx_ptr = NULL;
@@ -1631,6 +1631,15 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
if (!ctx_ptr)
return -ENOMEM;
/* Enable CDE in FECS header. Default cde = 0, is disabled,
* so no need to do anything in else {}
*/
if (c->cde) {
cde_v = gk20a_mem_rd32(ctx_ptr + ctxsw_prog_main_image_ctl_o(), 0);
cde_v |= ctxsw_prog_main_image_ctl_cde_enabled_f();
gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_ctl_o(), 0, cde_v);
}
for (i = 0; i < gr->ctx_vars.golden_image_size / 4; i++)
gk20a_mem_wr32(ctx_ptr, i, gr->ctx_vars.local_golden_image[i]);

12
drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h
View File

@@ -58,6 +58,18 @@ static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
{
return 0x00000008;
}
static inline u32 ctxsw_prog_main_image_ctl_o(void)
{
return 0x0000000c;
}
static inline u32 ctxsw_prog_main_image_ctl_cde_enabled_f(void)
{
return 0x400;
}
static inline u32 ctxsw_prog_main_image_ctl_cde_disabled_f(void)
{
return 0x0;
}
static inline u32 ctxsw_prog_main_image_patch_count_o(void)
{
return 0x00000010;