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gpu: nvgpu: Remove Pascal replayable fault support
We do not utilize or test replayable page faults in Pascal. Remove the code related to that. JIRA NVGPU-714 Change-Id: I2415bde347f8b018ebf99c3f9038d47c649d9464 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769697 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
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mobile promotions
mobile promotions
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59f07dcdc5
commit
6d8d5eb177
@@ -257,7 +257,6 @@ nvgpu-y += \
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gp10b/fb_gp10b.o \
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gp10b/pmu_gp10b.o \
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gp10b/hal_gp10b.o \
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gp10b/rpfb_gp10b.o \
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gp10b/regops_gp10b.o \
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gp10b/therm_gp10b.o \
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gp10b/fecs_trace_gp10b.o \
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@@ -156,7 +156,6 @@ srcs := common/mm/nvgpu_allocator.c \
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gp10b/fb_gp10b.c \
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gp10b/pmu_gp10b.c \
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gp10b/hal_gp10b.c \
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gp10b/rpfb_gp10b.c \
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gp10b/regops_gp10b.c \
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gp10b/therm_gp10b.c \
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gp10b/fecs_trace_gp10b.c \
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@@ -30,9 +30,7 @@
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#include "gk20a/gk20a.h"
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#include "gm20b/mm_gm20b.h"
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#include "mm_gp10b.h"
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#include "rpfb_gp10b.h"
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#include <nvgpu/hw/gp10b/hw_fb_gp10b.h>
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#include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
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#include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h>
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@@ -392,7 +390,6 @@ void gp10b_remove_bar2_vm(struct gk20a *g)
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{
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struct mm_gk20a *mm = &g->mm;
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gp10b_replayable_pagefault_buffer_deinit(g);
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nvgpu_free_inst_block(g, &mm->bar2.inst_block);
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nvgpu_vm_put(mm->bar2.vm);
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}
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@@ -1,158 +0,0 @@
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/*
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* GP10B RPFB
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*
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* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/dma.h>
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#include "gk20a/gk20a.h"
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#include "rpfb_gp10b.h"
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#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
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#include <nvgpu/hw/gp10b/hw_fb_gp10b.h>
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#include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h>
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int gp10b_replayable_pagefault_buffer_init(struct gk20a *g)
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{
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u32 addr_lo;
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u32 addr_hi;
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struct vm_gk20a *vm = g->mm.bar2.vm;
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int err;
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size_t rbfb_size = NV_UVM_FAULT_BUF_SIZE *
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fifo_replay_fault_buffer_size_hw_entries_v();
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nvgpu_log_fn(g, " ");
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if (!g->mm.bar2_desc.gpu_va) {
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err = nvgpu_dma_alloc_map_sys(vm, rbfb_size,
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&g->mm.bar2_desc);
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if (err) {
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nvgpu_err(g, "Error in replayable fault buffer");
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return err;
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}
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}
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addr_lo = u64_lo32(g->mm.bar2_desc.gpu_va >> 12);
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addr_hi = u64_hi32(g->mm.bar2_desc.gpu_va);
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gk20a_writel(g, fifo_replay_fault_buffer_hi_r(),
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fifo_replay_fault_buffer_hi_base_f(addr_hi));
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gk20a_writel(g, fifo_replay_fault_buffer_lo_r(),
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fifo_replay_fault_buffer_lo_base_f(addr_lo) |
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fifo_replay_fault_buffer_lo_enable_true_v());
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nvgpu_log_fn(g, "done");
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return 0;
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}
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void gp10b_replayable_pagefault_buffer_deinit(struct gk20a *g)
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{
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struct vm_gk20a *vm = g->mm.bar2.vm;
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nvgpu_dma_unmap_free(vm, &g->mm.bar2_desc);
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}
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u32 gp10b_replayable_pagefault_buffer_get_index(struct gk20a *g)
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{
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u32 get_idx = 0;
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nvgpu_log_fn(g, " ");
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get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r());
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if (get_idx >= fifo_replay_fault_buffer_size_hw_entries_v())
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nvgpu_err(g, "Error in replayable fault buffer");
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nvgpu_log_fn(g, "done");
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return get_idx;
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}
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u32 gp10b_replayable_pagefault_buffer_put_index(struct gk20a *g)
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{
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u32 put_idx = 0;
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nvgpu_log_fn(g, " ");
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put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r());
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if (put_idx >= fifo_replay_fault_buffer_size_hw_entries_v())
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nvgpu_err(g, "Error in UVM");
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nvgpu_log_fn(g, "done");
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return put_idx;
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}
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bool gp10b_replayable_pagefault_buffer_is_empty(struct gk20a *g)
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{
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u32 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r());
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u32 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r());
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return (get_idx == put_idx ? true : false);
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}
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bool gp10b_replayable_pagefault_buffer_is_full(struct gk20a *g)
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{
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u32 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r());
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u32 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r());
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u32 hw_entries = gk20a_readl(g, fifo_replay_fault_buffer_size_r());
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return (get_idx == ((put_idx + 1) % hw_entries) ? true : false);
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}
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bool gp10b_replayable_pagefault_buffer_is_overflow(struct gk20a *g)
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{
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u32 info = gk20a_readl(g, fifo_replay_fault_buffer_info_r());
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return fifo_replay_fault_buffer_info_overflow_f(info);
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}
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void gp10b_replayable_pagefault_buffer_clear_overflow(struct gk20a *g)
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{
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u32 info = gk20a_readl(g, fifo_replay_fault_buffer_info_r());
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info |= fifo_replay_fault_buffer_info_overflow_clear_v();
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gk20a_writel(g, fifo_replay_fault_buffer_info_r(), info);
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}
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/*
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* Debug function.
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*/
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void gp10b_replayable_pagefault_buffer_info(struct gk20a *g)
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{
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nvgpu_info(g, "rpfb low: 0x%x\n",
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gk20a_readl(g, fifo_replay_fault_buffer_lo_r()) >> 12);
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nvgpu_info(g, "rpfb hi: 0x%x\n",
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gk20a_readl(g, fifo_replay_fault_buffer_hi_r()));
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nvgpu_info(g, "rpfb enabled: 0x%x\n",
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gk20a_readl(g, fifo_replay_fault_buffer_lo_r()) & 0x1);
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nvgpu_info(g, "rpfb size: %d\n",
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gk20a_readl(g, fifo_replay_fault_buffer_size_r()));
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nvgpu_info(g, "rpfb get index: %d\n",
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gp10b_replayable_pagefault_buffer_get_index(g));
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nvgpu_info(g, "rpfb put index: %d\n",
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gp10b_replayable_pagefault_buffer_put_index(g));
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nvgpu_info(g, "rpfb empty: %d\n",
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gp10b_replayable_pagefault_buffer_is_empty(g));
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nvgpu_info(g, "rpfb full %d\n",
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gp10b_replayable_pagefault_buffer_is_full(g));
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nvgpu_info(g, "rpfb overflow %d\n",
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gp10b_replayable_pagefault_buffer_is_overflow(g));
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}
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@@ -1,39 +0,0 @@
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/*
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef RPFB_GP20B_H
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#define RPFB_GP20B_H
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struct gk20a;
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#define NV_UVM_FAULT_BUF_SIZE 32
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int gp10b_replayable_pagefault_buffer_init(struct gk20a *g);
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u32 gp10b_replayable_pagefault_buffer_get_index(struct gk20a *g);
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u32 gp10b_replayable_pagefault_buffer_put_index(struct gk20a *g);
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bool gp10b_replayable_pagefault_buffer_is_empty(struct gk20a *g);
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bool gp10b_replayable_pagefault_buffer_is_full(struct gk20a *g);
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bool gp10b_replayable_pagefault_buffer_is_overflow(struct gk20a *g);
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void gp10b_replayable_pagefault_buffer_clear_overflow(struct gk20a *g);
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void gp10b_replayable_pagefault_buffer_info(struct gk20a *g);
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void gp10b_replayable_pagefault_buffer_deinit(struct gk20a *g);
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#endif
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