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gpu: nvgpu: Fix MISRA 10.4 violations in nvlink

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MISRA Rule 10.4 requires operands of arithmetic operation to have
same essential type category. Fix such 10.4 violations in nvlink code
by adding "U" at the end of the integer literals. In some cases where
possible, replace the magic constants with functions returning
register constants.

JIRA NVGPU-1921

Change-Id: I070b6bcf879a4b18a0599ccda16834f7fdbd8d53
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2022990
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2019-02-19 17:50:30 +05:30
committed by mobile promotions
parent 7f5b7db97e
commit 6dbfd06fd4
4 changed files with 58 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/gpu/nvgpu/common/nvlink/intr_and_err_handling_gv100.c
View File

@@ -37,16 +37,16 @@
* The manuals are missing some useful defines
* we add them for now
*/
#define IPT_INTR_CONTROL_LINK(i) (nvlipt_intr_control_link0_r() + (i)*4)
#define IPT_ERR_UC_STATUS_LINK(i) (nvlipt_err_uc_status_link0_r() + (i)*36)
#define IPT_ERR_UC_MASK_LINK(i) (nvlipt_err_uc_mask_link0_r() + (i)*36)
#define IPT_ERR_UC_SEVERITY_LINK(i) (nvlipt_err_uc_severity_link0_r() + (i)*36)
#define IPT_ERR_UC_FIRST_LINK(i) (nvlipt_err_uc_first_link0_r() + (i)*36)
#define IPT_ERR_UC_ADVISORY_LINK(i) (nvlipt_err_uc_advisory_link0_r() + (i)*36)
#define IPT_ERR_C_STATUS_LINK(i) (nvlipt_err_c_status_link0_r() + (i)*36)
#define IPT_ERR_C_MASK_LINK(i) (nvlipt_err_c_mask_link0_r() + (i)*36)
#define IPT_ERR_C_FIRST_LINK(i) (nvlipt_err_c_first_link0_r() + (i)*36)
#define IPT_ERR_CONTROL_LINK(i) (nvlipt_err_control_link0_r() + (i)*4)
#define IPT_INTR_CONTROL_LINK(i) (nvlipt_intr_control_link0_r() + (i)*4U)
#define IPT_ERR_UC_STATUS_LINK(i) (nvlipt_err_uc_status_link0_r() + (i)*36U)
#define IPT_ERR_UC_MASK_LINK(i) (nvlipt_err_uc_mask_link0_r() + (i)*36U)
#define IPT_ERR_UC_SEVERITY_LINK(i) (nvlipt_err_uc_severity_link0_r() + (i)*36U)
#define IPT_ERR_UC_FIRST_LINK(i) (nvlipt_err_uc_first_link0_r() + (i)*36U)
#define IPT_ERR_UC_ADVISORY_LINK(i) (nvlipt_err_uc_advisory_link0_r() + (i)*36U)
#define IPT_ERR_C_STATUS_LINK(i) (nvlipt_err_c_status_link0_r() + (i)*36U)
#define IPT_ERR_C_MASK_LINK(i) (nvlipt_err_c_mask_link0_r() + (i)*36U)
#define IPT_ERR_C_FIRST_LINK(i) (nvlipt_err_c_first_link0_r() + (i)*36U)
#define IPT_ERR_CONTROL_LINK(i) (nvlipt_err_control_link0_r() + (i)*4U)
#define IPT_ERR_UC_ACTIVE_BITS (nvlipt_err_uc_status_link0_dlprotocol_f(1) | \
nvlipt_err_uc_status_link0_datapoisoned_f(1) | \
@@ -169,9 +169,9 @@ bool gv100_nvlink_minion_falcon_isr(struct gk20a *g)
if (intr & minion_falcon_irqstat_exterr_true_f()) {
nvgpu_err(g, "FALCON EXT ADDR: 0x%x 0x%x 0x%x",
MINION_REG_RD32(g, 0x244),
MINION_REG_RD32(g, 0x248),
MINION_REG_RD32(g, 0x24c));
MINION_REG_RD32(g, minion_falcon_csberrstat_r()),
MINION_REG_RD32(g, minion_falcon_csberr_info_r()),
MINION_REG_RD32(g, minion_falcon_csberr_addr_r()));
}
MINION_REG_WR32(g, minion_falcon_irqsclr_r(), intr);
@@ -182,7 +182,7 @@ bool gv100_nvlink_minion_falcon_isr(struct gk20a *g)
intr = MINION_REG_RD32(g, minion_falcon_irqstat_r()) &
MINION_REG_RD32(g, minion_falcon_irqmask_r());
return (intr == 0);
return (intr == 0U);
}
/*
@@ -270,7 +270,7 @@ static bool gv100_nvlink_minion_isr(struct gk20a *g) {
intr = MINION_REG_RD32(g, minion_minion_intr_r()) &
MINION_REG_RD32(g, minion_minion_intr_stall_en_r());
return (intr == 0);
return (intr == 0U);
}
/*

10
drivers/gpu/nvgpu/common/nvlink/nvlink.c
View File

@@ -203,13 +203,13 @@ int nvgpu_nvlink_set_sublink_mode(struct gk20a *g,
/* Extract a WORD from the MINION ucode */
u32 nvgpu_nvlink_minion_extract_word(struct nvgpu_firmware *fw, u32 idx)
{
u32 out_data = 0;
u8 byte = 0;
u32 i = 0;
u32 out_data = 0U;
u8 byte = 0U;
u32 i = 0U;
for (i = 0; i < 4; i++) {
for (i = 0U; i < 4U; i++) {
byte = fw->data[idx + i];
out_data |= ((u32)byte) << (8 * i);
out_data |= ((u32)byte) << (8U * i);
}
return out_data;

41
drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c
View File

@@ -182,7 +182,7 @@ static int gv100_nvlink_minion_load(struct gk20a *g)
break;
}
nvgpu_usleep_range(delay, delay * 2);
nvgpu_usleep_range(delay, delay * 2U);
delay = min_t(unsigned int,
delay << 1, GR_IDLE_CHECK_MAX);
} while (nvgpu_timeout_expired_msg(&timeout,
@@ -220,9 +220,10 @@ static int gv100_nvlink_minion_command_complete(struct gk20a *g, u32 link_id)
do {
reg = MINION_REG_RD32(g, minion_nvlink_dl_cmd_r(link_id));
if (minion_nvlink_dl_cmd_ready_v(reg) == 1) {
if (minion_nvlink_dl_cmd_ready_v(reg) == 1U) {
/* Command completed, check sucess */
if (minion_nvlink_dl_cmd_fault_v(reg) == 1) {
if (minion_nvlink_dl_cmd_fault_v(reg) ==
minion_nvlink_dl_cmd_fault_fault_clear_v()) {
nvgpu_err(g, "minion cmd(%d) error: 0x%x",
link_id, reg);
@@ -236,7 +237,7 @@ static int gv100_nvlink_minion_command_complete(struct gk20a *g, u32 link_id)
/* Commnand success */
break;
}
nvgpu_usleep_range(delay, delay * 2);
nvgpu_usleep_range(delay, delay * 2U);
delay = min_t(unsigned int,
delay << 1, GR_IDLE_CHECK_MAX);
@@ -481,8 +482,8 @@ static int gv100_nvlink_state_load_hal(struct gk20a *g)
return gv100_nvlink_minion_load(g);
}
#define TRIM_SYS_NVLINK_CTRL(i) (trim_sys_nvlink0_ctrl_r() + 16*i)
#define TRIM_SYS_NVLINK_STATUS(i) (trim_sys_nvlink0_status_r() + 16*i)
#define TRIM_SYS_NVLINK_CTRL(i) (trim_sys_nvlink0_ctrl_r() + 16U*i)
#define TRIM_SYS_NVLINK_STATUS(i) (trim_sys_nvlink0_status_r() + 16U*i)
int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask)
{
@@ -490,8 +491,8 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask)
u32 link_id;
u32 links_off;
struct nvgpu_timeout timeout;
u32 pad_ctrl = 0;
u32 swap_ctrl = 0;
u32 pad_ctrl = 0U;
u32 swap_ctrl = 0U;
u32 pll_id;
unsigned long bit;
@@ -542,7 +543,7 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask)
for_each_set_bit(bit, &link_mask, NVLINK_MAX_LINKS_SW) {
link_id = (u32)bit;
reg = gk20a_readl(g, TRIM_SYS_NVLINK_STATUS(link_id));
if (trim_sys_nvlink0_status_pll_off_v(reg) == 0) {
if (trim_sys_nvlink0_status_pll_off_v(reg) == 0U) {
links_off &= ~BIT32(link_id);
}
}
@@ -737,7 +738,7 @@ static int gv100_nvlink_rxcal_en(struct gk20a *g, unsigned long mask)
reg = DLPL_REG_RD32(g, link_id,
nvl_br0_cfg_status_cal_r());
if (nvl_br0_cfg_status_cal_rxcal_done_v(reg) == 1) {
if (nvl_br0_cfg_status_cal_rxcal_done_v(reg) == 1U) {
break;
}
nvgpu_udelay(5);
@@ -807,8 +808,8 @@ int gv100_nvlink_discover_link(struct gk20a *g)
u32 ioctrl_info_entry_type;
u32 ioctrl_discovery_size;
bool is_chain = false;
u8 nvlink_num_devices = 0;
unsigned long available_links = 0;
u8 nvlink_num_devices = 0U;
unsigned long available_links = 0UL;
struct nvgpu_nvlink_device_list *device_table;
int err = 0;
unsigned long bit;
@@ -827,7 +828,7 @@ int gv100_nvlink_discover_link(struct gk20a *g)
}
if (ioctrl_info_entry_type == NVL_DEVICE(ioctrl)) {
ioctrl_entry_addr = g->nvlink.ioctrl_table[0].pri_base_addr + 4;
ioctrl_entry_addr = g->nvlink.ioctrl_table[0].pri_base_addr + 4U;
table_entry = gk20a_readl(g, ioctrl_entry_addr);
ioctrl_discovery_size = nvlinkip_discovery_common_ioctrl_length_v(table_entry);
nvgpu_log(g, gpu_dbg_nvlink, "IOCTRL size: %d", ioctrl_discovery_size);
@@ -843,9 +844,9 @@ int gv100_nvlink_discover_link(struct gk20a *g)
return -ENOMEM;
}
for (i = 0; i < ioctrl_discovery_size; i++) {
for (i = 0U; i < ioctrl_discovery_size; i++) {
ioctrl_entry_addr =
g->nvlink.ioctrl_table[0].pri_base_addr + 4*i;
g->nvlink.ioctrl_table[0].pri_base_addr + 4U*i;
table_entry = gk20a_readl(g, ioctrl_entry_addr);
nvgpu_log(g, gpu_dbg_nvlink, "parsing ioctrl %d: 0x%08x", i, table_entry);
@@ -1173,7 +1174,7 @@ int gv100_nvlink_discover_ioctrl(struct gk20a *g)
int ret = 0;
u32 i;
struct nvgpu_nvlink_ioctrl_list *ioctrl_table;
u32 ioctrl_num_entries = 0;
u32 ioctrl_num_entries = 0U;
if (g->ops.top.get_num_engine_type_entries) {
ioctrl_num_entries = g->ops.top.get_num_engine_type_entries(g,
@@ -1181,7 +1182,7 @@ int gv100_nvlink_discover_ioctrl(struct gk20a *g)
nvgpu_log_info(g, "ioctrl_num_entries: %d", ioctrl_num_entries);
}
if (ioctrl_num_entries == 0) {
if (ioctrl_num_entries == 0U) {
nvgpu_err(g, "No NVLINK IOCTRL entry found in dev_info table");
return -EINVAL;
}
@@ -1193,7 +1194,7 @@ int gv100_nvlink_discover_ioctrl(struct gk20a *g)
return -ENOMEM;
}
for (i = 0; i < ioctrl_num_entries; i++) {
for (i = 0U; i < ioctrl_num_entries; i++) {
struct nvgpu_device_info dev_info;
ret = g->ops.top.get_device_info(g, &dev_info,
@@ -1758,7 +1759,7 @@ int gv100_nvlink_early_init(struct gk20a *g)
g->ops.mc.reset(g, mc_reset_nvlink_mask);
err = g->ops.nvlink.discover_link(g);
if ((err != 0) || (g->nvlink.discovered_links == 0)) {
if ((err != 0) || (g->nvlink.discovered_links == 0U)) {
nvgpu_err(g, "No links available");
goto exit;
}
@@ -1795,7 +1796,7 @@ int gv100_nvlink_early_init(struct gk20a *g)
nvgpu_log(g, gpu_dbg_nvlink, "discovered_links = 0x%08x (combination)",
g->nvlink.discovered_links);
if (hweight32(g->nvlink.discovered_links) > 1) {
if (hweight32(g->nvlink.discovered_links) > 1U) {
nvgpu_err(g, "more than one link enabled");
err = -EINVAL;
goto nvlink_init_exit;

18
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -846,6 +846,10 @@ static inline u32 minion_nvlink_dl_cmd_fault_v(u32 r)
{
return (r >> 30U) & 0x1U;
}
static inline u32 minion_nvlink_dl_cmd_fault_fault_clear_v(void)
{
return 0x00000001U;
}
static inline u32 minion_nvlink_dl_cmd_ready_f(u32 v)
{
return (v & 0x1U) << 31U;
@@ -942,4 +946,16 @@ static inline u32 minion_nvlink_link_intr_state_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 minion_falcon_csberrstat_r(void)
{
return 0x00000244U;
}
static inline u32 minion_falcon_csberr_info_r(void)
{
return 0x00000248U;
}
static inline u32 minion_falcon_csberr_addr_r(void)
{
return 0x0000024cU;
}
#endif