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gpu: nvgpu: update doxygen comments for pmu

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update the doxygen comments for pmu unit.

Jira NVGPU-6234

Change-Id: I7b06479208e93d5a8715b51d2dfacba7be60c186
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2463947
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
mkumbar
2020-12-28 15:22:37 +05:30
committed by mobile promotions
parent 5aa2311a88
commit 6e22ebf9f8
2 changed files with 9 additions and 3 deletions
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8
drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -50,6 +50,7 @@ struct gops_pmu {
* for PMU unit.
*
* @return 0 in case of success, < 0 in case of failure.
* @retval -ENOMEM if memory allocation for ecc stats fails.
*/
int (*ecc_init)(struct gk20a *g);
@@ -147,6 +148,7 @@ struct gops_pmu {
* and interrupts if interrupt support is enabled.
*
* @return 0 in case of success, < 0 in case of failure.
* @retval -ETIMEDOUT if PMU engine reset times out.
*/
int (*pmu_reset)(struct gk20a *g);
@@ -206,6 +208,7 @@ struct gops_pmu {
* @return Chip specific PMU Engine Falcon base address.
* For GV11B, GV11B PMU Engine Falcon base address will be
* returned.
* @retval Chip specific PMU Engine Falcon base address.
*/
u32 (*falcon_base_addr)(void);
@@ -290,6 +293,7 @@ struct gops_pmu {
* transaction error caused by falcon2csb request.
*
* @return 0 in case of success, -EIO in case of failure.
* @retval -EIO in case of BAR0 error
*/
int (*bar0_error_status)(struct gk20a *g, u32 *bar0_status,
u32 *etype);
@@ -302,7 +306,7 @@ struct gops_pmu {
* Validate IMEM/DMEM memory integrity by checking ECC status
* followed IMEM/DEME error correction status check.
*
* return True if corrected else False.
* @return True if corrected else False.
*/
bool (*validate_mem_integrity)(struct gk20a *g);

4
drivers/gpu/nvgpu/include/nvgpu/pmu.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -494,6 +494,7 @@ void nvgpu_pmu_enable_irq(struct gk20a *g, bool enable);
* enabled.
*
* @return 0 in case of success, < 0 in case of failure.
* @retval -ETIMEDOUT if PMU engine reset times out.
*/
int nvgpu_pmu_reset(struct gk20a *g);
@@ -512,6 +513,7 @@ int nvgpu_pmu_reset(struct gk20a *g);
* unit. Initializes the isr_mutex.
*
* @return 0 in case of success, < 0 in case of failure.
* @retval -ENOMEM if memory allocation for struct #nvgpu_pmu fails.
*/
int nvgpu_pmu_early_init(struct gk20a *g);