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gpu: nvgpu: fix MISRA errors nvgpu.hal.fifo.ramin

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Rule 8.6 requires each identifier with external linkage to have exactly
one external definitions.
This patch fixes rule 8.6 violations in nvgpu/hal/fifo/ramin_gk20a.h.

Jira NVGPU-3821

Change-Id: Ie3d6ddea330b9e504bd2157bd853b9db5fb8bfc4
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2154375
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2019-07-16 15:06:38 -07:00
committed by mobile promotions
parent 9b7a8f0263
commit 6f21c665ce
1 changed files with 5 additions and 2 deletions
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7
drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h
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@@ -27,13 +27,16 @@
struct gk20a;
struct nvgpu_mem;
u32 gk20a_ramin_base_shift(void);
u32 gk20a_ramin_alloc_size(void);
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void gk20a_ramin_set_gr_ptr(struct gk20a *g,
struct nvgpu_mem *inst_block, u64 gpu_va);
void gk20a_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
u64 pdb_addr, struct nvgpu_mem *pdb_mem);
void gk20a_ramin_set_adr_limit(struct gk20a *g,
struct nvgpu_mem *inst_block, u64 va_limit);
u32 gk20a_ramin_base_shift(void);
u32 gk20a_ramin_alloc_size(void);
#endif
#endif /* NVGPU_RAMIN_GK20A_H */