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gpu: nvgpu: remove zbc reference from ltc hal

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Instead of passing the zbc struct in ltc hal function parameter, only
pass the color array, depth and stencil values.This avoids
to include zbc header in ltc files.

JIRA  NVGPU-1882

Change-Id: Ic3b33fbb34e2da604a3d1315851e469ba370a662
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019863
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-02-14 20:06:47 -08:00
committed by mobile promotions
parent c493342dc0
commit 6fa5c4efa3
7 changed files with 24 additions and 27 deletions
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15
drivers/gpu/nvgpu/common/ltc/ltc_gm20b.c
View File

@@ -401,20 +401,19 @@ int gm20b_determine_L2_size_bytes(struct gk20a *g)
* Sets the ZBC color for the passed index.
*/
void gm20b_ltc_set_zbc_color_entry(struct gk20a *g,
struct zbc_entry *color_val,
u32 *color_l2,
u32 index)
{
u32 i;
u32 real_index = index + GK20A_STARTOF_ZBC_TABLE;
nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index));
ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
for (i = 0;
i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) {
nvgpu_writel_check(g,
ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i),
color_val->color_l2[i]);
color_l2[i]);
}
}
@@ -422,17 +421,15 @@ void gm20b_ltc_set_zbc_color_entry(struct gk20a *g,
* Sets the ZBC depth for the passed index.
*/
void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g,
struct zbc_entry *depth_val,
u32 depth_val,
u32 index)
{
u32 real_index = index + GK20A_STARTOF_ZBC_TABLE;
nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index));
ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
nvgpu_writel_check(g,
ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(),
depth_val->depth);
depth_val);
}
void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)

7
drivers/gpu/nvgpu/common/ltc/ltc_gm20b.h
View File

@@ -1,7 +1,7 @@
/*
* GM20B L2
*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -30,16 +30,15 @@
struct gk20a;
struct gr_gk20a;
struct gpu_ops;
struct zbc_entry;
enum gk20a_cbc_op;
int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr);
int gm20b_determine_L2_size_bytes(struct gk20a *g);
void gm20b_ltc_set_zbc_color_entry(struct gk20a *g,
struct zbc_entry *color_val,
u32 *color_l2,
u32 index);
void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g,
struct zbc_entry *depth_val,
u32 depth_val,
u32 index);
void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr);
void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled);

10
drivers/gpu/nvgpu/common/ltc/ltc_gv11b.c
View File

@@ -1,7 +1,7 @@
/*
* GV11B LTC
*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -65,17 +65,15 @@ static void gv11b_ltc_report_ecc_error(struct gk20a *g, u32 ltc, u32 slice,
* Sets the ZBC stencil for the passed index.
*/
void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
struct zbc_entry *stencil_val,
u32 stencil_depth,
u32 index)
{
u32 real_index = index + GK20A_STARTOF_ZBC_TABLE;
nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index));
ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
nvgpu_writel_check(g,
ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(),
stencil_val->depth);
stencil_depth);
}
void gv11b_ltc_init_fs_state(struct gk20a *g)

4
drivers/gpu/nvgpu/common/ltc/ltc_gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,7 +25,7 @@
struct gk20a;
void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
struct zbc_entry *stencil_val,
u32 stencil_depth,
u32 index);
void gv11b_ltc_init_fs_state(struct gk20a *g);
void gv11b_ltc_intr_en_illegal_compstat(struct gk20a *g, bool enable);

6
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -2497,7 +2497,8 @@ int nvgpu_gr_zbc_add_color(struct gk20a *g, struct gr_gk20a *gr,
u32 i;
/* update l2 table */
g->ops.ltc.set_zbc_color_entry(g, color_val, index);
g->ops.ltc.set_zbc_color_entry(g, color_val->color_l2,
index + GK20A_STARTOF_ZBC_TABLE);
/* update local copy */
for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) {
@@ -2546,7 +2547,8 @@ int nvgpu_gr_zbc_add_depth(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *depth_val, u32 index)
{
/* update l2 table */
g->ops.ltc.set_zbc_depth_entry(g, depth_val, index);
g->ops.ltc.set_zbc_depth_entry(g, depth_val->depth,
index + GK20A_STARTOF_ZBC_TABLE);
/* update local copy */
gr->zbc_dep_tbl[index].depth = depth_val->depth;

3
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -1205,7 +1205,8 @@ int gv11b_gr_zbc_add_stencil(struct gk20a *g, struct gr_gk20a *gr,
/* update l2 table */
if (g->ops.ltc.set_zbc_s_entry != NULL) {
g->ops.ltc.set_zbc_s_entry(g, stencil_val, index);
g->ops.ltc.set_zbc_s_entry(g, stencil_val->depth,
index + GK20A_STARTOF_ZBC_TABLE);
}
/* update local copy */

6
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -207,13 +207,13 @@ struct gpu_ops {
int (*cbc_ctrl)(struct gk20a *g, enum gk20a_cbc_op op,
u32 min, u32 max);
void (*set_zbc_color_entry)(struct gk20a *g,
struct zbc_entry *color_val,
u32 *color_val_l2,
u32 index);
void (*set_zbc_depth_entry)(struct gk20a *g,
struct zbc_entry *depth_val,
u32 depth_val,
u32 index);
void (*set_zbc_s_entry)(struct gk20a *g,
struct zbc_entry *s_val,
u32 s_val,
u32 index);
void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr);
void (*set_enabled)(struct gk20a *g, bool enabled);