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gpu: nvgpu: disable/preempt TSG for hwpm update

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To update hwpm, we currently disable/preempt only one
channel without considering if channel could be part
of a TSG

Hence, use proper APIs to disable/preempt/enable which
will internally handle channel/TSG case

Bug 200203191

Change-Id: I329a3c02d635265775f2081abba8e047f491fe7d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1155838
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Deepak Nibade
2016-05-30 12:53:58 +05:30
committed by Terje Bergstrom
parent e4dc4adb3b
commit 6ff0d4e6eb
1 changed files with 11 additions and 7 deletions
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18
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -1677,12 +1677,16 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g,
return 0;
}
c->g->ops.fifo.disable_channel(c);
ret = c->g->ops.fifo.preempt_channel(c->g, c->hw_chid);
ret = gk20a_disable_channel_tsg(g, c);
if (ret) {
c->g->ops.fifo.enable_channel(c);
gk20a_err(dev_from_gk20a(g),
"failed to preempt channel\n");
gk20a_err(dev_from_gk20a(g), "failed to disable channel/TSG\n");
return ret;
}
ret = gk20a_fifo_preempt(g, c);
if (ret) {
gk20a_enable_channel_tsg(g, c);
gk20a_err(dev_from_gk20a(g), "failed to preempt channel/TSG\n");
return ret;
}
@@ -1757,7 +1761,7 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g,
gk20a_mem_end(g, gr_mem);
/* enable channel */
c->g->ops.fifo.enable_channel(c);
gk20a_enable_channel_tsg(g, c);
return 0;
cleanup_pm_buf:
@@ -1766,7 +1770,7 @@ cleanup_pm_buf:
gk20a_gmmu_free_attr(g, DMA_ATTR_NO_KERNEL_MAPPING, &pm_ctx->mem);
memset(&pm_ctx->mem, 0, sizeof(struct mem_desc));
c->g->ops.fifo.enable_channel(c);
gk20a_enable_channel_tsg(g, c);
return ret;
}