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gpu: nvgpu: add priv_ring.intr_retrigger HAL
Add a priv_ring.intr_retrigger HAL for chips that need to retrigger pending interrupts in the PRIV_RING ISR. Jira NVGPU-9217 Change-Id: I976f26a39d148a0ce1ad54b53d982dc0af58197b Signed-off-by: Austin Tajiri <atajiri@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2839756 Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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@@ -1,7 +1,7 @@
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/*
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/*
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* GP10B priv ring
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* GP10B priv ring
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*
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*
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* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* copy of this software and associated documentation files (the "Software"),
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@@ -240,4 +240,8 @@ void gp10b_priv_ring_isr(struct gk20a *g)
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if (retries == 0U) {
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if (retries == 0U) {
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nvgpu_err(g, "priv ringmaster intr ack failed");
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nvgpu_err(g, "priv ringmaster intr ack failed");
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}
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}
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if (g->ops.priv_ring.intr_retrigger != NULL) {
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g->ops.priv_ring.intr_retrigger(g);
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}
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}
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}
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* copy of this software and associated documentation files (the "Software"),
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@@ -167,6 +167,21 @@ struct gops_priv_ring {
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void (*isr_handle_1)(struct gk20a *g, u32 status1);
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void (*isr_handle_1)(struct gk20a *g, u32 status1);
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/**
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* @brief Writes the unit level INTR_RETRIGGER register.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function writes the INTR_RETRIGGER register to handle the case
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* in which an interrupt is triggered between reading the interrupt
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* status register and clearing the interrupts. In this case, the rolled
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* up OR of pending interrupts will not change from 0 to 1, so an
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* interrupt message would not be sent to GIN. Writing to INTR_RETRIGGER
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* ensures that a new message is sent to GIN.
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*/
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void (*intr_retrigger)(struct gk20a *g);
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/**
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/**
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* @brief Returns number of enumerated Level Two Cache (LTC) chiplets.
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* @brief Returns number of enumerated Level Two Cache (LTC) chiplets.
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*
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*
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