gpu: nvgpu: skip pramin barriers for page tables

Page table updates have an explicit write barrier at the end of a pte
update operation in update_gmmu_ptes_locked(), so the per-wr32 wmb()s
are not necessary.

Jira DNVGPU-23

Change-Id: I2e2596f0900d840fadb369ee1261c5e2305f2070
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1225150
(cherry picked from commit 6664a667ea326e9663a6b502765f858d8669f4d9)
Reviewed-on: http://git-master/r/1227475
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/gk20a/mm_gk20a.c

@@ -1375,6 +1375,7 @@ static int gk20a_zalloc_gmmu_page_table(struct vm_gk20a *vm,
 	if (err)
 		return err;
 	entry->pgsz = pgsz_idx;
+	entry->mem.skip_wmb = true;
 
 	return err;
 }