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gpu: nvgpu: drop fifo_ in channel HAL names

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Now that the moved HAL ops from fifo are in channel, rename the
implementations to match.

Jira NVGPU-1307

Change-Id: I7b9336f506c9e71bcd0af98886216958bd6695eb
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017264
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Holtta
2019-02-12 13:05:19 +02:00
committed by mobile promotions
parent c04ad92cd1
commit 7189630e7c
15 changed files with 43 additions and 43 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/common/fifo/channel_gk20a.c
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@@ -31,14 +31,14 @@
#include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
void gk20a_fifo_channel_enable(struct channel_gk20a *ch)
void gk20a_channel_enable(struct channel_gk20a *ch)
{
gk20a_writel(ch->g, ccsr_channel_r(ch->chid),
gk20a_readl(ch->g, ccsr_channel_r(ch->chid)) |
ccsr_channel_enable_set_true_f());
}
void gk20a_fifo_channel_disable(struct channel_gk20a *ch)
void gk20a_channel_disable(struct channel_gk20a *ch)
{
gk20a_writel(ch->g, ccsr_channel_r(ch->chid),
gk20a_readl(ch->g,
@@ -46,7 +46,7 @@ void gk20a_fifo_channel_disable(struct channel_gk20a *ch)
ccsr_channel_enable_clr_true_f());
}
void gk20a_fifo_channel_unbind(struct channel_gk20a *ch)
void gk20a_channel_unbind(struct channel_gk20a *ch)
{
struct gk20a *g = ch->g;

6
drivers/gpu/nvgpu/common/fifo/channel_gk20a.h
View File

@@ -26,8 +26,8 @@
struct channel_gk20a;
struct gk20a;
void gk20a_fifo_channel_enable(struct channel_gk20a *ch);
void gk20a_fifo_channel_disable(struct channel_gk20a *ch);
void gk20a_fifo_channel_unbind(struct channel_gk20a *ch);
void gk20a_channel_enable(struct channel_gk20a *ch);
void gk20a_channel_disable(struct channel_gk20a *ch);
void gk20a_channel_unbind(struct channel_gk20a *ch);
#endif /* FIFO_CHANNEL_GK20A_H */

4
drivers/gpu/nvgpu/common/fifo/channel_gm20b.c
View File

@@ -32,7 +32,7 @@
#include <nvgpu/hw/gm20b/hw_ccsr_gm20b.h>
#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
void gm20b_fifo_channel_bind(struct channel_gk20a *c)
void gm20b_channel_bind(struct channel_gk20a *c)
{
struct gk20a *g = c->g;
@@ -59,7 +59,7 @@ void gm20b_fifo_channel_bind(struct channel_gk20a *c)
nvgpu_atomic_set(&c->bound, true);
}
u32 gm20b_fifo_channel_count(struct gk20a *g)
u32 gm20b_channel_count(struct gk20a *g)
{
return ccsr_channel__size_1_v();
}

4
drivers/gpu/nvgpu/common/fifo/channel_gm20b.h
View File

@@ -28,7 +28,7 @@
struct channel_gk20a;
struct gk20a;
void gm20b_fifo_channel_bind(struct channel_gk20a *c);
u32 gm20b_fifo_channel_count(struct gk20a *g);
void gm20b_channel_bind(struct channel_gk20a *c);
u32 gm20b_channel_count(struct gk20a *g);
#endif /* FIFO_CHANNEL_GM20B_H */

2
drivers/gpu/nvgpu/common/fifo/channel_gv100.c
View File

@@ -24,7 +24,7 @@
#include <nvgpu/hw/gv100/hw_ccsr_gv100.h>
u32 gv100_fifo_channel_count(struct gk20a *g)
u32 gv100_channel_count(struct gk20a *g)
{
return ccsr_channel__size_1_v();
}

2
drivers/gpu/nvgpu/common/fifo/channel_gv100.h
View File

@@ -27,6 +27,6 @@
struct gk20a;
u32 gv100_fifo_channel_count(struct gk20a *g);
u32 gv100_channel_count(struct gk20a *g);
#endif /* FIFO_CHANNEL_GV100_H */

4
drivers/gpu/nvgpu/common/fifo/channel_gv11b.c
View File

@@ -31,7 +31,7 @@
#include <nvgpu/hw/gv11b/hw_ccsr_gv11b.h>
void gv11b_fifo_channel_unbind(struct channel_gk20a *ch)
void gv11b_channel_unbind(struct channel_gk20a *ch)
{
struct gk20a *g = ch->g;
@@ -49,7 +49,7 @@ void gv11b_fifo_channel_unbind(struct channel_gk20a *ch)
}
}
u32 gv11b_fifo_channel_count(struct gk20a *g)
u32 gv11b_channel_count(struct gk20a *g)
{
return ccsr_channel__size_1_v();
}

4
drivers/gpu/nvgpu/common/fifo/channel_gv11b.h
View File

@@ -28,7 +28,7 @@
struct channel_gk20a;
struct gk20a;
void gv11b_fifo_channel_unbind(struct channel_gk20a *ch);
u32 gv11b_fifo_channel_count(struct gk20a *g);
void gv11b_channel_unbind(struct channel_gk20a *ch);
u32 gv11b_channel_count(struct gk20a *g);
#endif /* FIFO_CHANNEL_GV11B_H */

10
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -572,11 +572,11 @@ static const struct gpu_ops gm20b_ops = {
.runlist_write_state = gk20a_fifo_runlist_write_state,
},
.channel = {
.bind = gm20b_fifo_channel_bind,
.unbind = gk20a_fifo_channel_unbind,
.enable = gk20a_fifo_channel_enable,
.disable = gk20a_fifo_channel_disable,
.count = gm20b_fifo_channel_count,
.bind = gm20b_channel_bind,
.unbind = gk20a_channel_unbind,
.enable = gk20a_channel_enable,
.disable = gk20a_channel_disable,
.count = gm20b_channel_count,
},
.netlist = {
.get_netlist_name = gm20b_netlist_get_name,

10
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -625,11 +625,11 @@ static const struct gpu_ops gp10b_ops = {
.runlist_write_state = gk20a_fifo_runlist_write_state,
},
.channel = {
.bind = gm20b_fifo_channel_bind,
.unbind = gk20a_fifo_channel_unbind,
.enable = gk20a_fifo_channel_enable,
.disable = gk20a_fifo_channel_disable,
.count = gm20b_fifo_channel_count,
.bind = gm20b_channel_bind,
.unbind = gk20a_channel_unbind,
.enable = gk20a_channel_enable,
.disable = gk20a_channel_disable,
.count = gm20b_channel_count,
},
.netlist = {
.get_netlist_name = gp10b_netlist_get_name,

10
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -794,11 +794,11 @@ static const struct gpu_ops gv100_ops = {
.runlist_write_state = gk20a_fifo_runlist_write_state,
},
.channel = {
.bind = gm20b_fifo_channel_bind,
.unbind = gv11b_fifo_channel_unbind,
.enable = gk20a_fifo_channel_enable,
.disable = gk20a_fifo_channel_disable,
.count = gv100_fifo_channel_count,
.bind = gm20b_channel_bind,
.unbind = gv11b_channel_unbind,
.enable = gk20a_channel_enable,
.disable = gk20a_channel_disable,
.count = gv100_channel_count,
},
.netlist = {
.get_netlist_name = gv100_netlist_get_name,

10
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -753,11 +753,11 @@ static const struct gpu_ops gv11b_ops = {
.runlist_write_state = gk20a_fifo_runlist_write_state,
},
.channel = {
.bind = gm20b_fifo_channel_bind,
.unbind = gv11b_fifo_channel_unbind,
.enable = gk20a_fifo_channel_enable,
.disable = gk20a_fifo_channel_disable,
.count = gv11b_fifo_channel_count,
.bind = gm20b_channel_bind,
.unbind = gv11b_channel_unbind,
.enable = gk20a_channel_enable,
.disable = gk20a_channel_disable,
.count = gv11b_channel_count,
},
.netlist = {
.get_netlist_name = gv11b_netlist_get_name,

10
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -825,11 +825,11 @@ static const struct gpu_ops tu104_ops = {
.runlist_write_state = gk20a_fifo_runlist_write_state,
},
.channel = {
.bind = gm20b_fifo_channel_bind,
.unbind = gv11b_fifo_channel_unbind,
.enable = gk20a_fifo_channel_enable,
.disable = gk20a_fifo_channel_disable,
.count = gv100_fifo_channel_count,
.bind = gm20b_channel_bind,
.unbind = gv11b_channel_unbind,
.enable = gk20a_channel_enable,
.disable = gk20a_channel_disable,
.count = gv100_channel_count,
},
.netlist = {
.get_netlist_name = tu104_netlist_get_name,

2
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -438,7 +438,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.unbind = vgpu_channel_unbind,
.enable = vgpu_channel_enable,
.disable = vgpu_channel_disable,
.count = gm20b_fifo_channel_count,
.count = gm20b_channel_count,
},
.netlist = {
.get_netlist_name = gp10b_netlist_get_name,

2
drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -513,7 +513,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.unbind = vgpu_channel_unbind,
.enable = vgpu_channel_enable,
.disable = vgpu_channel_disable,
.count = gv11b_fifo_channel_count,
.count = gv11b_channel_count,
},
.netlist = {
.get_netlist_name = gv11b_netlist_get_name,