gpu: nvgpu: remove call to tegra_get_chip_id()

tegra_get_chip_id is going to be deprecated soon and this patch removes
calls to it. Chip-ID is already read via DT and call to
tegra_get_chip_id() can be avoided by adding metadata to store the
Chip-ID information in struct gk20a_platform.

Bug 200524194
Bug 200551105

Change-Id: I5f9f5abf679cf9afe98840e20144d76eb0238426
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2236311
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Debarshi Dutta
2019-11-11 10:52:27 +05:30
committed by Alex Waterman
parent 48d713f569
commit 71bb9aae91
7 changed files with 31 additions and 9 deletions

View File

@@ -54,6 +54,16 @@ struct nvgpu_pci_gpios {
#define PCI_VBAR_PWR_OFF_DELAY_MS 2
#define PCI_PWR_OFF_DELAY_MS 2
enum tegra_chip_id {
TEGRA_124,
TEGRA_132,
TEGRA_210,
TEGRA_186,
TEGRA_194,
TEGRA_194_VGPU,
TEGRA_124_VGPU,
};
struct gk20a_platform {
/* Populated by the gk20a driver before probing the platform. */
struct gk20a *g;
@@ -264,6 +274,8 @@ struct gk20a_platform {
bool has_cde;
#endif
enum tegra_chip_id platform_chip_id;
/* soc name for finding firmware files */
const char *soc_name;

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@@ -203,19 +203,19 @@ static void gk20a_tegra_prescale(struct device *dev)
*
*/
static void gk20a_tegra_calibrate_emc(struct device *dev,
static void gk20a_tegra_calibrate_emc(struct gk20a_platform *platform,
struct gk20a_emc_params *emc_params)
{
enum tegra_chipid cid = tegra_get_chip_id();
enum tegra_chip_id cid = platform->platform_chip_id;
long gpu_bw, emc_bw;
/* store gpu bw based on soc */
switch (cid) {
case TEGRA210:
case TEGRA_210:
gpu_bw = TEGRA_GM20B_BW_PER_FREQ;
break;
case TEGRA124:
case TEGRA132:
case TEGRA_124:
case TEGRA_132:
gpu_bw = TEGRA_GK20A_BW_PER_FREQ;
break;
default:
@@ -552,7 +552,7 @@ static void gk20a_tegra_scale_init(struct device *dev)
return;
emc_params->freq_last_set = -1;
gk20a_tegra_calibrate_emc(dev, emc_params);
gk20a_tegra_calibrate_emc(platform, emc_params);
#ifdef CONFIG_TEGRA_BWMGR
emc_params->bwmgr_cl = tegra_bwmgr_register(TEGRA_BWMGR_CLIENT_GPU);
@@ -810,7 +810,7 @@ static int gk20a_tegra_probe(struct device *dev)
}
platform->g->clk.gpc_pll.id = GK20A_GPC_PLL;
if (tegra_get_chip_id() == TEGRA210) {
if (platform->platform_chip_id == TEGRA_210) {
/* WAR for bug 1547668: Disable railgating and scaling
irrespective of platform data if the rework was not made. */
np = of_find_node_by_path("/gpu-dvfs-rework");
@@ -823,7 +823,7 @@ static int gk20a_tegra_probe(struct device *dev)
platform->g->clk.gpc_pll.id = GM20B_GPC_PLL_C1;
}
if (tegra_get_chip_id() == TEGRA132)
if (platform->platform_chip_id == TEGRA_132)
platform->soc_name = "tegra13x";
gk20a_tegra_get_clocks(dev);
@@ -962,6 +962,7 @@ struct gk20a_platform gm20b_tegra_platform = {
.has_cde = true,
#endif
.platform_chip_id = TEGRA_210,
.soc_name = "tegra21x",
.unified_memory = true,

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@@ -489,6 +489,7 @@ struct gk20a_platform gp10b_tegra_platform = {
.force_reset_in_do_idle = false,
.platform_chip_id = TEGRA_186,
.soc_name = "tegra18x",
.unified_memory = true,

View File

@@ -305,6 +305,7 @@ struct gk20a_platform gv11b_tegra_platform = {
.dump_platform_dependencies = gk20a_tegra_debug_dump,
.platform_chip_id = TEGRA_194,
.soc_name = "tegra19x",
.honors_aperture = true,

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@@ -49,7 +49,10 @@ bool nvgpu_is_bpmp_running(struct gk20a *g)
bool nvgpu_is_soc_t194_a01(struct gk20a *g)
{
return ((tegra_get_chip_id() == TEGRA194 &&
struct device *dev = dev_from_gk20a(g);
struct gk20a_platform *platform = gk20a_get_platform(dev);
return ((platform->platform_chip_id == TEGRA_194 &&
tegra_chip_get_revision() == TEGRA194_REVISION_A01) ?
true : false);
}

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@@ -96,6 +96,8 @@ struct gk20a_platform gv11b_vgpu_tegra_platform = {
.clk_round_rate = vgpu_plat_clk_round_rate,
.get_clk_freqs = vgpu_plat_clk_get_freqs,
.platform_chip_id = TEGRA_194_VGPU,
/* frequency scaling configuration */
.devfreq_governor = "userspace",

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@@ -86,6 +86,8 @@ struct gk20a_platform vgpu_tegra_platform = {
.clk_round_rate = vgpu_plat_clk_round_rate,
.get_clk_freqs = vgpu_plat_clk_get_freqs,
.platform_chip_id = TEGRA_124_VGPU,
/* frequency scaling configuration */
.devfreq_governor = "userspace",