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gpu: nvgpu: post bpt events after processing

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Receive hww_global_esr in gr_gv11b_handle_sm_exception() and
pass it to gr_gk20a_handle_sm_exception()

Bug 200209410

Change-Id: I57a701a1f1fa560367f78db212c06d4ce361c7f0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1194987
GVS: Gerrit_Virtual_Submit
Reviewed-by: Cory Perry <cperry@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Deepak Nibade
2016-08-01 14:27:54 +05:30
committed by Terje Bergstrom
parent 32fe739f68
commit 7297e14019
1 changed files with 3 additions and 2 deletions
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5
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
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@@ -61,14 +61,15 @@ static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num)
}
static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
bool *post_event, struct channel_gk20a *fault_ch)
bool *post_event, struct channel_gk20a *fault_ch,
u32 *hww_global_esr)
{
int ret = 0;
u32 offset = proj_gpc_stride_v() * gpc +
proj_tpc_in_gpc_stride_v() * tpc;
u32 lrf_ecc_status, shm_ecc_status;
gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch);
gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr);
/* Check for LRF ECC errors. */
lrf_ecc_status = gk20a_readl(g,