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gpu: nvgpu: Fix MISRA 10.3 error in common.gr unit

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Fix MISRA C-2012 Rule 10.3 error in common.gr unit
misra_c_2012_rule_10_3_violation: Implicit conversion of
"!!(gr->ctxsw_disable_count < 0)" from essential type "boolean" to
different or narrower essential type "signed 32-bit int".

Jira NVGPU-3622

Change-Id: I27fb1aa64906242230678dff345307eb0a2d7bdc
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2140940
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-06-21 14:59:53 -07:00
committed by mobile promotions
parent 64937a1112
commit 72f0c22377
1 changed files with 2 additions and 1 deletions
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3
drivers/gpu/nvgpu/common/gr/gr.c
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@@ -22,6 +22,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/io.h>
#include <nvgpu/bug.h>
#include <nvgpu/unit.h>
#include <nvgpu/errno.h>
#include <nvgpu/safe_ops.h>
@@ -775,7 +776,7 @@ int nvgpu_gr_enable_ctxsw(struct gk20a *g)
goto ctxsw_already_enabled;
}
gr->ctxsw_disable_count--;
WARN_ON(gr->ctxsw_disable_count < 0);
nvgpu_assert(gr->ctxsw_disable_count >= 0);
if (gr->ctxsw_disable_count == 0) {
err = g->ops.gr.falcon.ctrl_ctxsw(g,
NVGPU_GR_FALCON_METHOD_CTXSW_START, 0U, NULL);