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gpu: nvgpu: gk20a_gr_isr code cleanup

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Simplify the interrupt handling code in gk20a_gr_isr.
There is no need to individually clear the handled interrupt bit.
Clear all interrupt bits set at the end with one register write.

Add two new hals
read_pending_interrupts  - read the gr interrupt register
clear_pending_interrupts - write to gr interrupt register the pending ones.

JIRA NVGPU-3016

Change-Id: Iea682524d767d0f9b82d1137a8c0358e65eabade
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2091086
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-04-05 16:36:57 -07:00
committed by mobile promotions
parent 9c465d5fd5
commit 744f0afcb2
9 changed files with 51 additions and 34 deletions
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10
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c
View File

@@ -31,6 +31,16 @@
#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
void gm20b_gr_intr_clear_pending_interrupts(struct gk20a *g, u32 gr_intr)
{
nvgpu_writel(g, gr_intr_r(), gr_intr);
}
u32 gm20b_gr_intr_read_pending_interrupts(struct gk20a *g)
{
return nvgpu_readl(g, gr_intr_r());
}
bool gm20b_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception)
{
bool gpc_reset = false;

2
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.h
View File

@@ -30,6 +30,8 @@ struct nvgpu_gr_config;
struct nvgpu_gr_tpc_exception;
struct nvgpu_gr_isr_data;
void gm20b_gr_intr_clear_pending_interrupts(struct gk20a *g, u32 gr_intr);
u32 gm20b_gr_intr_read_pending_interrupts(struct gk20a *g);
bool gm20b_gr_intr_handle_exceptions(struct gk20a *g, bool *is_gpc_exception);
u32 gm20b_gr_intr_read_gpc_tpc_exception(u32 gpc_exception);
u32 gm20b_gr_intr_read_gpc_exception(struct gk20a *g, u32 gpc);