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Simplify the interrupt handling code in gk20a_gr_isr. There is no need to individually clear the handled interrupt bit. Clear all interrupt bits set at the end with one register write. Add two new hals read_pending_interrupts - read the gr interrupt register clear_pending_interrupts - write to gr interrupt register the pending ones. JIRA NVGPU-3016 Change-Id: Iea682524d767d0f9b82d1137a8c0358e65eabade Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2091086 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>