gpu: nvgpu: Added PSTATE-3.5 version support

Add Pstate table version(0x60) and base entry size(0x5)


JIRA NVGPU-1242

Change-Id: If575372bbf7560ab511be32a0c65dbf1eb3ad232
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1849348
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2018-10-18 11:02:19 +05:30
committed by mobile promotions
parent 5ad253cee7
commit 74baefc6f1
2 changed files with 6 additions and 2 deletions

View File

@@ -545,6 +545,7 @@ struct vfield_entry {
#define PERF_CLK_DOMAINS_IDX_INVALID PERF_CLK_DOMAINS_IDX_MAX
#define VBIOS_PSTATE_TABLE_VERSION_5X 0x50U
#define VBIOS_PSTATE_TABLE_VERSION_6X 0x60U
#define VBIOS_PSTATE_HEADER_5X_SIZE_10 (10U)
struct vbios_pstate_header_5x {
@@ -564,6 +565,7 @@ u8 cpi_features;
#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2 0x2U
#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3 0x3U
#define VBIOS_PSTATE_BASE_ENTRY_6X_SIZE_5 0x5U
struct vbios_pstate_entry_clock_5x {
u16 param0;

View File

@@ -403,7 +403,8 @@ static int parse_pstate_table_5x(struct gk20a *g,
if ((hdr->header_size != VBIOS_PSTATE_HEADER_5X_SIZE_10) ||
(hdr->base_entry_count == 0) ||
((hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2) &&
(hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3)) ||
(hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3) &&
(hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_6X_SIZE_5)) ||
(hdr->clock_entry_size != VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6) ||
(hdr->clock_entry_count > CLK_SET_INFO_MAX_SIZE)) {
return -EINVAL;
@@ -474,7 +475,8 @@ static int pstate_sw_setup(struct gk20a *g)
goto done;
}
if (hdr->version != VBIOS_PSTATE_TABLE_VERSION_5X) {
if (hdr->version != VBIOS_PSTATE_TABLE_VERSION_5X &&
hdr->version != VBIOS_PSTATE_TABLE_VERSION_6X) {
nvgpu_err(g, "unknown/unsupported clocks table version=0x%02x",
hdr->version);
err = -EINVAL;