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gpu: nvgpu: skip security check in ctxsw init

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Force ctxsw ucode to skip the security level check by clearing mailbox 1
before starting FECS/GPCCS.

Jira NVGPU-9217

Change-Id: Id4286d0882a29a849128e62c5421c8ae6071e3b1
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2891013
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Austin Tajiri
2023-04-19 18:37:35 +00:00
committed by mobile promotions
parent 7e0351f291
commit 7522c3ee31
1 changed files with 7 additions and 1 deletions
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8
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -199,6 +199,12 @@ void gm20b_gr_falcon_start_ucode(struct gk20a *g)
g->ops.gr.falcon.fecs_ctxsw_clear_mailbox(g, 0U, (~U32(0U))); g->ops.gr.falcon.fecs_ctxsw_clear_mailbox(g, 0U, (~U32(0U)));
/*
* When GPCCS and FECS are booted in NS mode, clear mailbox 1 to skip
* the security level check in ucode.
*/
g->ops.gr.falcon.fecs_ctxsw_clear_mailbox(g, 1U, (~U32(0U)));
nvgpu_writel(g, gr_gpccs_dmactl_r(), gr_gpccs_dmactl_require_ctx_f(0U)); nvgpu_writel(g, gr_gpccs_dmactl_r(), gr_gpccs_dmactl_require_ctx_f(0U));
nvgpu_writel(g, gr_fecs_dmactl_r(), gr_fecs_dmactl_require_ctx_f(0U)); nvgpu_writel(g, gr_fecs_dmactl_r(), gr_fecs_dmactl_require_ctx_f(0U));