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synced 2025-12-22 09:12:24 +03:00
gpu: nvgpu: Remove the GPU-NEXT conditional
Remove build conditional for GPU-NEXT. It was used for including code for tu104, but now it's part of main nvgpu. Leave a TURING conditional to not need Turing code in other builds. JIRA NVGPU-961 Change-Id: I74177863c451d78b6db6165249561f15eadc3cc3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1936803 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -147,7 +147,7 @@ config NVGPU_USE_TEGRA_ALLOC_FD
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It is only available in Tegra kernel.
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config TEGRA_GPU_NEXT
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config NVGPU_SUPPORT_TURING
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bool "Turing family GPU"
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depends on GK20A && ARCH_TEGRA_19x_SOC
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default y
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@@ -26,6 +26,7 @@ nvgpu-y += common/bus/bus_gk20a.o \
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common/bus/bus_gm20b.o \
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common/bus/bus_gp10b.o \
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common/bus/bus_gv100.o \
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common/bus/bus_tu104.o \
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common/priv_ring/priv_ring_gm20b.o \
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common/priv_ring/priv_ring_gp10b.o \
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common/ptimer/ptimer.o \
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@@ -35,6 +36,7 @@ nvgpu-y += common/bus/bus_gk20a.o \
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common/fb/fb_gp106.o \
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common/fb/fb_gv11b.o \
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common/fb/fb_gv100.o \
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common/fb/fb_tu104.o \
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common/perf/perf_gm20b.o \
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common/perf/perf_gv11b.o \
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common/perf/perfbuf.o \
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@@ -53,13 +55,27 @@ nvgpu-y += common/bus/bus_gk20a.o \
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common/mc/mc_gp10b.o \
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common/mc/mc_gv11b.o \
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common/mc/mc_gv100.o \
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common/mc/mc_tu104.o \
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common/sync/channel_sync.o \
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common/sync/channel_sync_semaphore.o \
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common/boardobj/boardobj.o \
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common/boardobj/boardobjgrp.o \
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common/boardobj/boardobjgrpmask.o \
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common/boardobj/boardobjgrp_e255.o \
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common/boardobj/boardobjgrp_e32.o
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common/boardobj/boardobjgrp_e32.o \
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common/ltc/ltc.o \
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common/ltc/ltc_gm20b.o \
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common/ltc/ltc_gp10b.o \
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common/ltc/ltc_gv11b.o \
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common/ltc/ltc_tu104.o \
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common/netlist/netlist.o \
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common/netlist/netlist_sim.o \
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common/netlist/netlist_gm20b.o \
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common/netlist/netlist_gp106.o \
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common/netlist/netlist_gp10b.o \
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common/netlist/netlist_gv100.o \
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common/netlist/netlist_gv11b.o \
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common/netlist/netlist_tu104.o
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# Linux specific parts of nvgpu.
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nvgpu-y += \
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@@ -101,7 +117,8 @@ nvgpu-y += \
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os/linux/nvlink.o \
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os/linux/dt.o \
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os/linux/ecc_sysfs.o \
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os/linux/ltc.o
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os/linux/ltc.o \
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os/linux/os_ops_tu104.o
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nvgpu-$(CONFIG_GK20A_VIDMEM) += \
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os/linux/dmabuf_vidmem.o
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@@ -222,18 +239,6 @@ nvgpu-y += \
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common/pmu/pmu_pg.o \
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common/pmu/pmu_perfmon.o \
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common/pmu/pmu_debug.o \
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common/netlist/netlist.o \
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common/netlist/netlist_sim.o \
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common/netlist/netlist_gm20b.o \
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common/netlist/netlist_gp106.o \
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common/netlist/netlist_gp10b.o \
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common/netlist/netlist_gv100.o \
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common/netlist/netlist_gv11b.o \
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common/netlist/netlist_tu104.o \
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common/ltc/ltc.o \
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common/ltc/ltc_gm20b.o \
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common/ltc/ltc_gp10b.o \
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common/ltc/ltc_gv11b.o \
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common/sec2/sec2.o \
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common/sec2/sec2_ipc.o \
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common/io_common.o \
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@@ -344,6 +349,19 @@ nvgpu-y += \
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gv100/pmu_gv100.o \
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gv100/perf_gv100.o \
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gv100/gsp_gv100.o \
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gv100/clk_gv100.o \
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tu104/hal_tu104.o \
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tu104/fifo_tu104.o \
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tu104/gr_tu104.o \
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tu104/func_tu104.o \
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tu104/bios_tu104.o \
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tu104/nvlink_tu104.o \
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tu104/fbpa_tu104.o \
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tu104/flcn_tu104.o \
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tu104/sec2_tu104.o \
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tu104/ecc_tu104.o \
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tu104/regops_tu104.o \
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tu104/acr_tu104.o \
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pstate/pstate.o \
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clk/clk_vin.o \
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clk/clk_fll.o \
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@@ -372,28 +390,4 @@ nvgpu-y += \
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therm/thrmchannel.o \
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therm/thrmpmu.o \
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lpwr/rppg.o \
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lpwr/lpwr.o \
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gv100/clk_gv100.o
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nvgpu-$(CONFIG_TEGRA_GPU_NEXT) += \
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common/bus/bus_tu104.o \
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common/fb/fb_tu104.o \
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common/ltc/ltc_tu104.o \
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common/mc/mc_tu104.o
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nvgpu-$(CONFIG_TEGRA_GPU_NEXT) += \
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tu104/hal_tu104.o \
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tu104/fifo_tu104.o \
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tu104/gr_tu104.o \
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tu104/func_tu104.o \
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tu104/bios_tu104.o \
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tu104/nvlink_tu104.o \
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tu104/fbpa_tu104.o \
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tu104/flcn_tu104.o \
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tu104/sec2_tu104.o \
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tu104/ecc_tu104.o \
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tu104/regops_tu104.o \
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tu104/acr_tu104.o
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nvgpu-$(CONFIG_TEGRA_GPU_NEXT) += \
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os/linux/os_ops_tu104.o
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lpwr/lpwr.o
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@@ -33,9 +33,7 @@
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#include "gp106/hal_gp106.h"
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#include "gv100/hal_gv100.h"
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#include "gv11b/hal_gv11b.h"
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#if defined(CONFIG_TEGRA_GPU_NEXT)
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#include "nvgpu_gpuid_next.h"
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#endif
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#include "tu104/hal_tu104.h"
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int nvgpu_init_hal(struct gk20a *g)
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{
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@@ -80,9 +78,9 @@ int nvgpu_init_hal(struct gk20a *g)
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return -ENODEV;
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}
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break;
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#if defined(CONFIG_TEGRA_GPU_NEXT)
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case NVGPU_GPUID_NEXT:
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if (NVGPU_NEXT_INIT_HAL(g) != 0) {
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#if defined(CONFIG_NVGPU_SUPPORT_TURING)
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case NVGPU_GPUID_TU104:
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if (tu104_init_hal(g) != 0) {
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return -ENODEV;
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}
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break;
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@@ -24,14 +24,13 @@
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#include <nvgpu/netlist.h>
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#include "netlist_tu104.h"
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#include "nvgpu_gpuid_next.h"
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int tu104_netlist_get_name(struct gk20a *g, int index, char *name)
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{
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u32 ver = g->params.gpu_arch + g->params.gpu_impl;
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switch (ver) {
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case NVGPU_GPUID_NEXT:
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case NVGPU_GPUID_TU104:
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(void) sprintf(name, "%s/%s", "tu104", "NETC_img.bin");
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break;
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default:
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@@ -35,7 +35,7 @@
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#define NVGPU_PMU_NS_UCODE_IMAGE "gpmu_ucode.bin"
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/* PMU F/W version */
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#define APP_VERSION_GPU_NEXT 24408680U
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#define APP_VERSION_TU10X 24408680U
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#define APP_VERSION_GV11B 25005711U
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#define APP_VERSION_GV10X 24283706U
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#define APP_VERSION_GP10X 24076634U
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@@ -1228,7 +1228,7 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
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break;
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case APP_VERSION_GV11B:
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case APP_VERSION_GV10X:
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case APP_VERSION_GPU_NEXT:
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case APP_VERSION_TU10X:
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g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
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pg_cmd_eng_buf_load_size_v2;
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g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
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@@ -1294,7 +1294,7 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
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g->ops.pmu_ver.pmu_allocation_get_fb_size =
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pmu_allocation_get_fb_size_v3;
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if (pmu->desc->app_version == APP_VERSION_GV10X ||
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pmu->desc->app_version == APP_VERSION_GPU_NEXT) {
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pmu->desc->app_version == APP_VERSION_TU10X) {
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g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
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get_pmu_init_msg_pmu_queue_params_v5;
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g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
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@@ -38,11 +38,9 @@
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#include "gp106/acr_gp106.h"
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#include "gp106/pmu_gp106.h"
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#include "gv100/acr_gv100.h"
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#include "tu104/acr_tu104.h"
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#include "sec2_gp106.h"
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#if defined(CONFIG_TEGRA_GPU_NEXT)
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#include "nvgpu_gpuid_next.h"
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#endif
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#include <nvgpu/hw/gp106/hw_psec_gp106.h>
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#include <nvgpu/hw/gp106/hw_pwr_gp106.h>
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@@ -214,13 +212,11 @@ int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
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GV100_FECS_UCODE_SIG,
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NVGPU_REQUEST_FIRMWARE_NO_SOC);
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break;
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#if defined(CONFIG_TEGRA_GPU_NEXT)
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case NVGPU_GPUID_NEXT:
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case NVGPU_GPUID_TU104:
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fecs_sig = nvgpu_request_firmware(g,
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NVGPU_GPU_NEXT_FECS_UCODE_SIG,
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TU104_FECS_UCODE_SIG,
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NVGPU_REQUEST_FIRMWARE_NO_SOC);
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break;
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#endif
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default:
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nvgpu_err(g, "no support for GPUID %x", ver);
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}
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@@ -318,13 +314,11 @@ int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
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GV100_GPCCS_UCODE_SIG,
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NVGPU_REQUEST_FIRMWARE_NO_SOC);
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break;
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#if defined(CONFIG_TEGRA_GPU_NEXT)
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case NVGPU_GPUID_NEXT:
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case NVGPU_GPUID_TU104:
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gpccs_sig = nvgpu_request_firmware(g,
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NVGPU_GPU_NEXT_GPCCS_UCODE_SIG,
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TU104_GPCCS_UCODE_SIG,
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NVGPU_REQUEST_FIRMWARE_NO_SOC);
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break;
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#endif
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default:
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nvgpu_err(g, "no support for GPUID %x", ver);
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}
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@@ -1793,6 +1793,7 @@ int gk20a_wait_for_idle(struct gk20a *g);
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#define NVGPU_GPUID_GP106 0x00000136
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#define NVGPU_GPUID_GV11B 0x0000015B
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#define NVGPU_GPUID_GV100 0x00000140
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#define NVGPU_GPUID_TU104 0x00000164
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int gk20a_init_gpu_characteristics(struct gk20a *g);
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@@ -1,39 +0,0 @@
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/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GPUID_NEXT_H
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#define NVGPU_GPUID_NEXT_H
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#define NVGPU_GPUID_NEXT 0x00000164
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#define NVGPU_GPU_NEXT_FECS_UCODE_SIG "tu104/fecs_sig.bin"
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#define NVGPU_GPU_NEXT_GPCCS_UCODE_SIG "tu104/gpccs_sig.bin"
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#define NVGPU_NEXT_INIT_HAL tu104_init_hal
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#define NVGPU_NEXT_INIT_OS_OPS nvgpu_tu104_init_os_ops
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struct nvgpu_os_linux;
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extern int tu104_init_hal(struct gk20a *g);
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extern void nvgpu_tu104_init_os_ops(struct nvgpu_os_linux *l);
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#endif /* NVGPU_GPUID_NEXT_H */
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@@ -21,10 +21,7 @@
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#include "os_ops_gp106.h"
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#include "os_ops_gv11b.h"
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#include "os_ops_gv100.h"
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#if defined(CONFIG_TEGRA_GPU_NEXT)
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#include "nvgpu_gpuid_next.h"
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#endif
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#include "os_ops_tu104.h"
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int nvgpu_init_os_linux_ops(struct nvgpu_os_linux *l)
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{
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@@ -48,11 +45,9 @@ int nvgpu_init_os_linux_ops(struct nvgpu_os_linux *l)
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case NVGPU_GPUID_GV11B:
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nvgpu_gv11b_init_os_ops(l);
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break;
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#if defined(CONFIG_TEGRA_GPU_NEXT)
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case NVGPU_GPUID_NEXT:
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NVGPU_NEXT_INIT_OS_OPS(l);
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case NVGPU_GPUID_TU104:
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nvgpu_tu104_init_os_ops(l);
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break;
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#endif
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default:
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break;
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}
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@@ -17,6 +17,6 @@
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#ifndef __LINUX_OS_OPS_TU104_H
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#define __LINUX_OS_OPS_TU104_H
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void nvgpu_tu104_init_os_ops(struct nvgpu_os_linux *l)
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void nvgpu_tu104_init_os_ops(struct nvgpu_os_linux *l);
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#endif
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@@ -25,6 +25,9 @@
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#define TU104_MAX_SUPPORTED_LSFM 4
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#define TU104_FECS_UCODE_SIG "tu104/fecs_sig.bin"
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#define TU104_GPCCS_UCODE_SIG "tu104/gpccs_sig.bin"
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void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
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#endif /*NVGPU_ACR_TU104_H*/
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